LDMOS Well Structure for Higher Breakdown and Lower On-Resistance
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving higher breakdown voltage and lower on-resistance, particularly in lateral double-diffused metal oxide semiconductor field effect transistors (LDMOS), which are used as power switching devices.
Innovation Solution
A method for manufacturing a semiconductor device involves forming a deep well of a second conductivity type in a semiconductor substrate, creating a channel region, a first well region, and a drift region of a first conductivity type, and incorporating ion implantation regions to form an NPNP structure without the need for epitaxial growth or buried layers, enhancing the depletion effect and isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional LDMOS structure is used, then manufacturing process is simple, but breakdown voltage is limited and on-resistance is high
Solution Approach 1:
The patent implements a nested well structure where a first well region (N-type) is formed within a deep well (P-type), which itself is formed in a semiconductor substrate (N-type). This nested configuration creates multiple conductivity type layers that enhance the breakdown voltage through improved depletion region management while maintaining compatibility with standard CMOS fabrication processes.
Solution Approach 2:
The patent applies local quality by creating regions with different conductivity types and doping concentrations at specific locations. The deep well provides localized P-type doping in the N-type substrate, while the first well region provides localized N-type doping, creating optimal electric field distribution locally to enhance breakdown voltage without affecting the entire device structure.
2Reliability
If additional processes like epitaxial growth and buried layer formation are added, then breakdown voltage increases, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges the functions of multiple separate processes into a unified well formation approach. By forming the deep well and first well region using sequential ion implantation and thermal diffusion steps within the existing CMOS process flow, the patent achieves the breakdown voltage enhancement that would traditionally require separate epitaxial growth and buried layer formation processes, thereby reducing overall manufacturing complexity.
Solution Approach 2:
The well regions are formed using in-situ ion implantation and thermal diffusion processes that utilize the existing semiconductor substrate and standard process equipment. The structure self-organizes through controlled doping diffusion during thermal processing steps already present in the CMOS fabrication sequence, eliminating the need for additional specialized process equipment or steps.
3Reliability
If well regions are spaced closer to channel, then on-resistance decreases, but isolation and depletion effect are reduced
Solution Approach 1:
The patent optimizes the spacing parameters between the channel region and well regions to achieve the optimal balance. By carefully controlling the lateral distance and vertical depth of the deep well and first well region, the patent positions these regions close enough to reduce on-resistance through better carrier transport while maintaining sufficient spacing to preserve the depletion effect and electrical isolation, thereby achieving optimal performance through parameter optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a semiconductor device with improved breakdown voltage and reduced on-resistance, simplifying the manufacturing process and reducing costs by eliminating the need for additional processes like epitaxial growth and buried layer formation.
Implementation Method 1
forming an ion implantation region of the first conductivity type in the deep well of the second conductivity type, the ion implantation region of the first conductivity type being located under the drift region of the second conductivity type
Data Source
AI summary
A method for manufacturing a semiconductor device, and a semiconductor device. The method includes: providing a semiconductor substrate of a first conductivity type, forming a deep well of a second conductivity type in the semiconductor substrate, forming a channel region of the first conductivity type, a first well region of the first conductivity type, and a drift region of the second conductivity type in the deep well, the first well region and the channel region being spaced by a portion of the deep well, the drift region being located between the channel region and the first well region, forming an ion implantation region of the first conductivity type in the deep well, the ion implantation region being located under the drift region, and forming a source region of the second conductivity type and a drain region of the second conductivity type in the deep well.