High-Voltage LDMOSFET Deep Well for CMOS Breakdown Voltage
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Solution Overview
Problem
As device geometries shrink, existing high-voltage LDMOSFETs face challenges in maintaining high breakdown voltages in standard CMOS processes, necessitating improved high-voltage switching devices for applications like charge pumps and display drivers.
Innovation Solution
The development of a high-voltage LDMOSFET with a semiconductor substrate featuring a gate well region, source and drain well regions with insulating layers, and a deep well region that communicates with the biasing well to extend under the source and drain regions, along with biasing contacts to bias the deep well and gate well, while using trench isolation and LOCOS-based schemes for insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device geometries are shrunk to improve integration density, then productivity and integration density are improved, but breakdown voltage capability deteriorates
Solution Approach 1:
The patent introduces a deep well region extending vertically beneath the source and drain regions, adding a depth dimension to the device structure. This deep well configuration allows the breakdown voltage to be determined by the deep well-to-substrate junction rather than the lateral dimensions, enabling high voltage capability in scaled devices.
Solution Approach 2:
The device structure is segmented into multiple regions: a surface well region containing the channel and shallow junctions, and a deep well region extending beneath. This segmentation allows the surface region to be optimized for transistor operation while the deep region provides high voltage breakdown characteristics, resolving the contradiction between scaling and voltage capability.
2Ease of manufacture
If conventional LDMOSFET structures are used in standard CMOS, then ease of manufacture is improved, but breakdown voltage capability deteriorates due to shallow junctions
Solution Approach 1:
The deep well region is formed within the standard CMOS substrate, nesting the high-voltage structure inside the conventional process framework. The deep well extends beneath the standard well regions, allowing high voltage functionality to be embedded within standard CMOS architecture without requiring separate fabrication lines.
Solution Approach 2:
Instead of relying on lateral diffusion lengths to achieve breakdown voltage, the patent uses vertical depth of the deep well region. This dimensional transition from lateral to vertical control enables high breakdown voltage while maintaining compatibility with standard planar CMOS processing techniques.
3Reliability
If deep well regions are added to enhance breakdown voltage, then reliability is improved, but device complexity increases
Solution Approach 1:
The deep well region serves multiple functions: it provides the high breakdown voltage path, acts as a substrate isolation layer, and enables both high voltage and standard voltage devices to coexist on the same chip. This multi-functionality reduces the need for additional separate structures, offsetting the initial complexity addition.
Solution Approach 2:
The patent merges the high voltage device structure with standard CMOS devices by forming the deep well region that accommodates both types of devices. The same deep well structure provides breakdown protection for LDMOSFETs while standard CMOS devices operate in the upper regions, combining multiple device types into a unified structure.
Data Source
AI summary
A high-voltage LDMOSFET includes a semiconductor substrate, in which a gate well is formed. A source well and a drain well are formed on either side of the gate well, and include insulating regions within them that do not reach the full depth. An insulating layer is disposed on the substrate, covering the gate well and a portion of the source well and the drain well. A conductive gate is disposed on the insulating layer. Biasing wells are formed adjacent the source well and the drain well. A deep well is formed in the substrate such that it communicates with the biasing wells and the gate well, while extending under the source well and the drain well, such as to avoid them. Biasing contacts at the top of the biasing wells bias the deep well, and therefore also the gate well.