LDMOSFET Drain Drift Region Linear Grading via Mask Segmentation
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Solution Overview
Problem
Current planar lateral double-diffused metal oxide semiconductor field effect transistors (LDMOSFETs) face challenges in reducing 'ON' resistance (Ron) and improving manufacturability, with existing doping techniques resulting in non-linearly graded dopant profiles and size disparities between P-type and N-type LDMOSFETs.
Innovation Solution
A method involving a unique mask with specific opening patterns for dopant implantation, followed by annealing, to achieve a linearly graded conductivity level in the drain drift region, allowing for reduced Ron and improved manufacturability by using the same mask and implant levels for both N-type and P-type LDMOSFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional doping techniques are used to form drain drift regions, then the manufacturing process is simple, but the dopant profile is non-linearly graded resulting in higher ON resistance
Solution Approach 1:
The mask pattern is segmented into multiple distinct opening types (first openings, second openings, third openings) with different geometries and positions. Each opening type corresponds to a specific region of the drain drift region, enabling precise spatial control of dopant implantation to achieve linear grading while maintaining manufacturing feasibility through modular mask design
Solution Approach 2:
Different regions of the drain drift region are assigned different local qualities through the mask pattern: the first region receives dopant through first openings with specific characteristics, the second region through second openings, and the third region through third openings. This local differentiation enables the dopant concentration to vary linearly across the region, achieving the desired graded profile with controlled ON resistance
2Ease of manufacture
If separate mask and implant levels are used for P-type and N-type LDMOSFETs, then each device type can be optimized independently, but the manufacturing complexity and time increase
Solution Approach 1:
The mask pattern and implant level are designed with universal applicability to form drain drift regions for both P-type and N-type LDMOSFETs using the same manufacturing parameters. The pattern includes opening types that can be selectively activated or positioned to accommodate different device types, enabling a single mask design to serve multiple functions and eliminate the need for separate optimization processes
Solution Approach 2:
The manufacturing process merges the previously separate procedures for P-type and N-type LDMOSFET drain drift region formation into a single unified process. By combining the mask pattern design and implant level selection into one set of parameters that work for both device types, the process reduces manufacturing steps, time, and complexity while maintaining the ability to produce both device types with their respective optimizations
3Reliability
If the channel region is positioned closer to the source region than the drain region to achieve high blocking voltage, then the breakdown voltage increases, but the ON resistance increases due to longer channel length
Solution Approach 1:
The dopant concentration parameter in the drain drift region is changed through the mask pattern to achieve linear grading. By controlling the dopant concentration to increase linearly from the channel region toward the drain region, the electrical properties of the drain drift region are optimized to reduce ON resistance while maintaining the asymmetric channel positioning required for high blocking voltage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces 'ON' resistance and enhances manufacturability by achieving a linearly graded conductivity level, enabling smaller device sizes and equal resistance values for both P-type and N-type LDMOSFETs, thereby improving high-voltage operability and manufacturing efficiency.
Implementation Method 1
a mask can be formed on a semiconductor layer. The mask can have multiple openings that extend vertically to a region of the semiconductor layer... a dopant implant region having a given type conductivity at a level that increases essentially linearly from one side of the region to the other
Implementation Method 2
these methods employ a unique mask, which has openings arranged in a particular pattern... followed by annealing, to achieve a linearly graded conductivity level
Data Source
AI summary
Disclosed are methods that employ a mask with openings arranged in a pattern of elongated trenches and holes of varying widths to achieve a linearly graded conductivity level. These methods can be used to form a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) with a drain drift region having an appropriate type conductivity at a level that increases essentially linearly from the body region to the drain region. Furthermore, these methods also provide for improve manufacturability in that multiple instances of this same pattern can be used during a single dopant implant process to implant a first dopant with a first type (e.g., N-type) conductivity into the drain drift regions of both first and second type LDMOSFETs (e.g., N and P-type LDMOSFETs, respectively). In this case, the drain drift region of a second type LDMOSFET can subsequently be uniformly counter-doped. Also disclosed are the resulting semiconductor structures.