LDMOSFET Gate Structure Optimizing Breakdown Voltage
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to optimize the trench isolation process and improve trench morphology in LDMOSFET devices to enhance electric field distribution during breakdown, increase breakdown voltage, and reduce on-resistance (Ron) while maintaining constant device length and on-resistance.
Innovation Solution
A gate structure for semiconductor devices is developed, comprising a trench gate with a silicon oxide filler and a polysilicon control gate, a shield gate with a single or multiple segments, and a well region with doped regions, where the side wall silicon oxide thickness gradually increases, and a method involving trench definition, silicon oxide deposition, etching, and polysilicon filling to achieve optimal electric field distribution and reduced on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the trench isolation process is optimized to improve trench morphology, then the electric field distribution during breakdown is enhanced and breakdown voltage is increased, but the device length and on-resistance remain constant limiting further optimization
Solution Approach 1:
The gate structure is segmented into multiple functional components: trench gate, planar gate, control gate, and shield gate. This segmentation allows independent optimization of each component's morphology and electrical properties, enabling improved breakdown voltage through optimized trench structure without increasing overall device complexity
Solution Approach 2:
Different regions of the gate structure are given different local qualities: the trench gate region is optimized for breakdown voltage with specific morphology, while the planar gate region is optimized for low on-resistance. This local quality differentiation allows simultaneous optimization of multiple parameters without compromising overall device performance
2Reliability
If the trench morphology is improved to enhance electric field distribution, then breakdown voltage increases, but the on-resistance reduction space is limited by constant device length
Solution Approach 1:
The trench gate structure is formed with pre-optimized morphology through controlled oxidation and etching processes before subsequent doping and metallization steps. This preliminary action establishes the optimal electric field distribution foundation early in the manufacturing process, enabling high breakdown voltage while maintaining manufacturing precision through standardized process steps
3Reliability
If the device length is kept constant to maintain constant on-resistance, then the optimization space for reducing on-resistance is limited, but the breakdown voltage can be improved through trench optimization
Solution Approach 1:
The gate structure transitions from a conventional planar design to a three-dimensional configuration with trench gate, control gate, and shield gate components arranged in vertical and lateral dimensions. This dimensional change enables independent optimization of breakdown voltage through vertical trench structure while maintaining constant device length, effectively decoupling the optimization of these two parameters
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed gate structure and manufacturing method improve electric field distribution, increase breakdown voltage, and reduce on-resistance by optimizing trench morphology and carrier mobility, making it suitable for LDMOSFET devices and other semiconductor devices with trench gate structures.
Implementation Method 1
forming a silicon oxide corner structure at a top corner of the trench by thermal oxidizing
Implementation Method 2
depositing a nitrogenous compound at the wafer surface covering a surface of the silicon oxide in the trench
Implementation Method 3
forming a well region adjacent to the trench by implanting doped ions with a second conduction type
Data Source
AI summary
A gate structure of a semiconductor device, includes: a trench gate and a planar gate including a plurality of polysilicon structures (406) separated from each other; the gate structure of the semiconductor device further includes a well region (503) being adjacent to the trench gate and being disposed under the planar gate; a first conduction type doped region (504) being disposed in the well region (503) and including a plurality of regions separated from each other, wherein each region is disposed under adjacent polysilicon structures (406), and respective regions are electrically connected to the planar gate; and a source (504a) being disposed in the well region (503); wherein the trench gate includes: a silicon oxide filler (202) including a side wall silicon oxide and a bottom silicon oxide; a control gate (402) being located over the trench gate, wherein a side wall of the control gate is enclosed by the side wall silicon oxide, and the control gate (402) is electrically-connected to the planar gate; a shield gate (404) having a single segment structure or a longitudinally arranged multiple segments structure; and an insulation silicon oxide (204) being filled between adjacent control gate and shield gate in vertical direction.