LDMOSFET Recessed Source Structure for Parasitic BJT Suppression
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices, particularly LDMOSFETs, face challenges in improving performance due to the operation of parasitic bipolar transistors which reduce the on-state breakdown voltage and are difficult to miniaturize due to limitations in controlling the width of the p-type semiconductor region.
Innovation Solution
The semiconductor device incorporates a recessed portion in the substrate and a p-type semiconductor region formed under this recessed portion, which helps in suppressing the accumulation of holes at the PN junction, preventing parasitic bipolar transistor operation and allowing for a reduced size of the device by accurately controlling the impurity concentration and dimensions of the p-type semiconductor region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the width of the p-type semiconductor region is reduced to miniaturize the device, then the device size is reduced, but the control precision of the p-type semiconductor region width becomes difficult
Solution Approach 1:
A recessed portion is introduced as an intermediary structure between the source region and the first semiconductor region. This recessed portion serves as a physical mask and depth reference during ion implantation, enabling precise control of the p-type semiconductor region formation without requiring direct width control of the p-type region itself. The recessed portion width can be controlled with higher precision than the p-type region width, thus resolving the contradiction between miniaturization and manufacturing precision.
2Reliability
If the p-type semiconductor region is formed to suppress parasitic bipolar transistor operation, then the on-state breakdown voltage is improved, but the device size increases
Solution Approach 1:
The solution transitions from controlling the p-type semiconductor region in the lateral dimension to controlling it through the vertical dimension via the recessed portion. By forming the p-type region through ion implantation into the recessed portion, the effective width of the p-type region is reduced while maintaining its depth and functionality for suppressing parasitic bipolar transistors. This dimensional transformation allows simultaneous achievement of high breakdown voltage and small device size.
3Manufacturing precision
If the source region is formed by ion implantation, then the impurity concentration is improved, but holes accumulate at the PN junction causing parasitic bipolar transistor operation
Solution Approach 1:
The harmful effect of hole accumulation at the PN junction is addressed by extracting or removing the source region material in the recessed portion area. By forming a recessed portion that penetrates through the source region, holes that would normally accumulate at the PN junction are prevented from accumulating, thus suppressing parasitic bipolar transistor operation while maintaining the beneficial ion implantation characteristics of the source region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the on-state breakdown voltage and improves the overall performance of the semiconductor device while enabling miniaturization by effectively suppressing parasitic bipolar transistor operation and reducing the size of the p-type semiconductor region.
Implementation Method 1
forming a source region of a first conductivity type in the first upper surface by an ion implantation method; forming a first semiconductor region of a second conductivity type under the recessed portion in the semiconductor substrate by an ion implantation method
Data Source
AI summary
In a semiconductor substrate, an n-type source region, an n-type drain region, a first p-type semiconductor region, and a second p-type semiconductor region surrounding the n-type source region and the first p-type semiconductor region are formed. A gate electrode is formed on the semiconductor substrate between the n-type source region and the n-type drain region via a dielectric film GF. In the semiconductor substrate, a recessed portion is formed so as to penetrate through the n-type source region, and the first p-type semiconductor region is formed under the recessed portion.