LDO Regulator Buffer Drive Capability Adjustment
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Solution Overview
Problem
Low Drop-Out (LDO) regulator circuits face challenges in accurately reducing output voltage variations due to input voltage fluctuations, particularly at high frequencies, leading to phase delays and oscillations due to the inability of error amplifiers and buffer circuits to respond effectively.
Innovation Solution
The proposed linear regulator circuit includes an output transistor, an error amplifier, a buffer circuit, and a drive capability adjustment circuit that synchronizes with output current to adjust the load drive capability, utilizing P-channel MOS transistors and capacitors to reduce output voltage variations and enhance phase margin by varying the ON-resistance of transistors in response to output voltage changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the output current is increased, then the power delivery capability is improved, but the phase delay increases causing oscillation in the closed-loop
Solution Approach 1:
The buffer circuit dynamically adjusts its output drive capability based on the output current level. When output current increases, the buffer circuit enhances its drive capability to reduce phase delay and prevent oscillation, while maintaining stability across varying load conditions
Solution Approach 2:
The circuit changes the drive capability parameter of the buffer circuit in response to output current variations. This parameter adjustment allows the buffer to provide sufficient drive strength at high current levels without causing excessive phase delay, resolving the stability issue
2Speed
If the error amplifier and buffer circuit respond to high frequency output voltage variations, then the responsiveness is improved, but the phase delay increases causing oscillation
Solution Approach 1:
The buffer circuit dynamically adjusts its drive capability based on operating conditions. At high frequencies with increased output current, the enhanced drive capability compensates for phase delay, maintaining responsiveness while preventing oscillation
3Reliability
If the transistor ON-resistance is varied to reduce PSRR peak, then the output voltage variation is reduced, but the drive capability adjustment becomes non-linear at low output voltages
Solution Approach 1:
The drive capability adjustment is segmented into two independent control mechanisms: one based on transistor ON-resistance variation for PSRR peak reduction, and another based on drive capability adjustment circuit for linear response. This segmentation allows each mechanism to operate optimally without interfering with the other's linearity
Solution Approach 2:
The drive capability adjustment circuit acts as an intermediary that provides linear control of the buffer output drive capability, independent of the non-linear ON-resistance variation. This intermediary ensures linear response even when transistor ON-resistance becomes non-linear at low output voltages
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces output voltage variations across both low and high frequency ranges, enhances the phase margin to prevent oscillations, and maintains a stable output voltage with reduced voltage drop relative to the input voltage, improving the circuit's responsiveness and stability.
Implementation Method 1
utilizing P-channel MOS transistors and capacitors to reduce output voltage variations and enhance phase margin by varying the ON-resistance of transistors in response to output voltage changes
Data Source
AI summary
According to one aspect of the embodiment, a linear regulator circuit includes an output transistor outputting an output current based on a input voltage, an error amplifier outputting a control signal based on an electric potential difference between an output voltage based on the output current and a reference voltage, a buffer circuit coupled between the error amplifier and the output transistor, and a drive capability adjustment circuit adjusting a load drive capability of the buffer circuit in synchronization with the output current.