LDO Buffer Circuit Using Differential Pair for Fast Stable Response
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Solution Overview
Problem
Low dropout voltage (LDO) linear voltage regulators face challenges in achieving fast transient response while maintaining high DC output voltage accuracy and low quiescent current, often leading to loop stability issues due to the limitations of super source follower (SSF) buffer circuits, which require the reference and output voltages to be in the same domain and have high current draw for stabilization.
Innovation Solution
The proposed solution involves a buffer circuit design that operates in separate voltage domains using a FET differential pair instead of a source follower, reducing quiescent current and allowing for separate voltage domains, along with a pseudo-ESR implementation using high voltage FETs to enhance stability and phase margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a super source follower (SSF) buffer circuit is used to achieve fast transient response, then the transient response speed is improved, but the quiescent current increases and loop stability problems occur
Solution Approach 1:
The patent changes the fundamental operating parameters of the buffer circuit by transitioning from a source follower topology to a folded cascode topology. This parameter change enables the circuit to achieve fast transient response through the cascode structure's inherent speed while simultaneously reducing quiescent current through optimized current mirroring and biasing schemes. The folded cascode configuration allows for lower operating currents while maintaining high bandwidth and fast response characteristics.
2Speed
If a super source follower (SSF) buffer circuit is used to achieve fast transient response, then the transient response speed is improved, but loop stability problems occur
Solution Approach 1:
The patent introduces an intermediary compensation capacitor in parallel with the feedback resistor of the folded cascode buffer circuit. This intermediary element serves as a stability compensation mechanism that addresses the loop stability issues inherent in high-speed buffer designs. The capacitor provides phase compensation and pole-zero cancellation that stabilizes the feedback loop while preserving the fast transient response characteristics of the folded cascode topology.
3Device complexity
If the reference and output voltages are required to be in the same domain in SSF buffer circuits, then circuit simplicity is maintained, but adaptability to separate voltage domains is limited
Solution Approach 1:
The patent segments the voltage domains by introducing separate reference voltage and output voltage domains in the folded cascode buffer circuit. The circuit is divided into distinct functional blocks that can operate at different voltage levels, with the error amplifier operating at one voltage domain and the output stage operating at another. This segmentation enables the LDO regulator to handle cases where the reference voltage and output voltage are in different domains, significantly improving adaptability while maintaining reasonable circuit complexity through modular design.
Data Source
AI summary
Described embodiments include a buffer circuit for a linear voltage regulator. A first transistor has first and second current terminals and a first control terminal. The first current terminal is coupled to an input voltage terminal. A second transistor is coupled between the input voltage terminal and an output voltage terminal, and has a second control terminal that is coupled to the first control terminal. A resistor is coupled between the second and fourth current terminals. A third transistor is coupled between the second current terminal and ground through a first current source. A fourth transistor is coupled between the fourth current terminal and ground through a second current source, and has a fourth control terminal coupled to the third control terminal and to the eighth current terminal.