LDO Regulator Cascode Circuit for PSR Stability
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Solution Overview
Problem
Low drop-out (LDO) regulators face challenges in minimizing power supply rejection (PSR) characteristics due to parasitic capacitance at the gate of the pass transistor, which can lead to deteriorated PSR characteristics and potential oscillations.
Innovation Solution
The implementation of a semiconductor circuit with a cascode connection circuit, mirror compensation capacitance, and an AC path capacitance between the input voltage node and the source of the NMOS transistor in the cascode connection circuit, which optimizes the PSR characteristics without shifting the power-supply conductance to the negative side.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parasitic capacitance is added to the gate of the pass transistor, then the LDO regulator can be implemented, but the PSR characteristics deteriorate
Solution Approach 1:
The patent introduces a cascode connection circuit as an intermediary structure between the pass transistor and the output. This cascode configuration acts as a buffer that isolates the parasitic capacitance effect at the gate from the output voltage, thereby improving PSR characteristics while maintaining the necessary LDO functionality.
Solution Approach 2:
The patent segments the single pass transistor structure into a multi-stage cascode configuration. By dividing the power transmission path into multiple transistor stages (first cascode transistor, second cascode transistor, and pass transistor), the patent reduces the impact of parasitic capacitance on the overall PSR performance.
2Reliability
If AC gain of gate signal is increased to improve PSR characteristics, then PSR improves, but power-supply conductance shifts to negative side causing oscillations
Solution Approach 1:
The patent carefully controls and optimizes the capacitance values of the compensation capacitors (C1 and C2) to achieve the desired AC gain improvement without pushing the power-supply conductance into the negative region. By adjusting these parameters within specific ranges, the patent achieves better PSR characteristics while maintaining output stability.
Solution Approach 2:
The patent implements a feedback mechanism through the cascode connection circuit and compensation capacitors that provides stable control of the gate signal. This feedback structure ensures that the AC gain is improved for better PSR characteristics while preventing the power-supply conductance from shifting to the negative side, thus avoiding oscillations.
3Reliability
If cascode connection circuit is added to improve PSR characteristics, then PSR improves, but device complexity increases
Solution Approach 1:
The cascode connection circuit in the patent serves multiple functions simultaneously: it improves PSR characteristics by isolating parasitic capacitance effects, provides voltage buffering, and maintains proper biasing for the pass transistor. This multi-functionality reduces the need for additional separate components, thereby limiting the increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively improves the PSR characteristics of the LDO regulator, preventing oscillations and maintaining stable output voltage even under fluctuating input voltage and load current conditions.
Implementation Method 1
a first capacitor connected between the second node and a fourth node of a first one of the plurality of second transistors
Implementation Method 2
a second capacitor connected between the first node and the fourth node
Data Source
AI summary
A semiconductor circuit includes: a first transistor connected between a first node configured to input an input voltage and a second node configured to output an output voltage; a cascode connection circuit including a plurality of second transistors connected in a cascode configuration between the first node and a third node set at a first voltage; a first capacitor connected between the second node and a fourth node of a first one of the plurality of second transistors; and a second capacitor connected between the first node and the fourth node, wherein a fifth node of the first second transistor is connected to a gate of the first transistor.