Dual-Path LDO Regulator With Charge Pump for Fast Low-Area Response
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Solution Overview
Problem
Existing voltage regulator circuits, such as low-dropout (LDO) regulators, face challenges in achieving fast response time, small silicon area, low standby and quiescent current consumption, and high current efficiency, especially in portable and battery-operated devices that require operation over a wide range of supply voltages and temperatures.
Innovation Solution
A circuit design that includes an input node, an output node, first and second feedback networks, a charge pump circuit, and pass elements, where the first feedback network produces a pulsed control signal and the second feedback network generates a threshold signal to control the charge pump and pass elements, enabling efficient voltage regulation with dynamic comparators and level shifters to manage voltage differences and current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional LDO regulator circuits are used, then voltage regulation is provided, but the response time is slow and silicon area is large
Solution Approach 1:
The regulator circuit is segmented into two independent paths: a fast transient response path using a first pass transistor for quick voltage adjustments, and a steady-state path using a second pass transistor for stable operation. This segmentation allows each path to be optimized independently, achieving fast response without requiring large compensation capacitors that would increase silicon area.
Solution Approach 2:
The circuit dynamically switches between two operational modes based on transient conditions. A transient detection mechanism activates the fast response path when voltage transients are detected, and deactivates it when steady-state conditions prevail. This dynamic adaptation enables fast response time only when needed, minimizing the silicon area required for compensation components.
2Adaptability or versatility
If LDO regulators are designed for wide voltage range operation, then adaptability is improved, but standby current and quiescent current increase
Solution Approach 1:
The regulator dynamically adjusts its operational parameters based on the input voltage level and load conditions. The transient response path is activated only when needed, and the circuit adapts its current consumption characteristics to match the operating conditions, enabling wide voltage range operation with minimized standby and quiescent current.
Solution Approach 2:
The circuit changes its operational parameters (such as pass transistor conductivity, feedback loop gain, and charge pump activation) based on the input voltage level. This allows the regulator to maintain high efficiency and low current consumption across a wide voltage range from 1.6V to 3.6V by optimizing parameters for each operating region.
3Speed
If fast response time is achieved through conventional methods, then speed is improved, but circuit complexity and silicon area increase
Solution Approach 1:
The control architecture is segmented into simple transient detection logic and two distinct pass transistor paths. Instead of using complex compensation networks and large capacitors, the invention uses a straightforward transient detection mechanism that triggers the fast response path, significantly reducing circuit complexity while achieving fast response time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a voltage regulator with fast response time, reduced silicon area, low current consumption, and high current efficiency, capable of operating effectively across a wide range of voltages and temperatures, suitable for memory devices and other applications.
Implementation Method 1
a charge pump circuit configured to produce a supply voltage higher than the input voltage
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
A low-dropout voltage regulator circuit (40) is disclosed. The regulator receives an input voltage (Vcc) at an input node (400) and produces a regulated output voltage (VREG) at an output node (402). A first feedback network (R1, 412, 414) produces a feedback signal (VFB) indicative of the output voltage (VREG), and compares the feedback signal to a reference signal (VREF) to assert and de-assert a first pulsed control signal (COMP_OU-T) when the reference signal is higher and lower, respectively, than the feedback signal. A time-averaged value of the first pulsed control signal is a function of the difference between the reference signal and the feedback signal. A second feedback network (R2, 418, 420) produces a threshold signal (VTH) indicative of the input voltage, and compares the output voltage (VREG) to the threshold signal to assert and de-assert a second control signal (VCC_EN) when the threshold signal is higher and lower, respectively, than the output voltage. A charge pump circuit (408) is enabled (PMP_EN) if the second control signal is de-asserted and is clocked by the first pulsed control signal to produce a supply voltage (VBL_SUPPLY) higher than the input voltage (Vcc). A first pass element (404a) arranged between the input node and the output node is enabled when the second control signal is asserted and is selectively activated when the first pulsed control signal is asserted. A second pass element (404b) arranged between the charge pump (408) and the output node (402) is selectively activated when the second control signal is de-asserted.