LDO Clamping Diode for NMOS Load Transient Response
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Solution Overview
Problem
Low dropout voltage regulators (LDOs) with NMOS output transistors face challenges in load transient response due to large voltage swings at internal nodes, leading to delayed current supply and output voltage transients, which can cause errors or system failures.
Innovation Solution
Incorporating a clamping diode between the output pin and internal nodes of the LDO to limit the voltage drop, ensuring the NMOS output transistor gate voltage remains close to the output voltage, thereby reducing the time required to enable the transistor and minimizing output transients.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clamping device is added to limit voltage swing at internal nodes, then load transient response is improved, but device complexity increases
Solution Approach 1:
A clamping device is introduced as an intermediary element between the output pin and the control input of the output driver. This clamping device comprises a first clamping diode with anode connected to the control input and cathode connected to the output pin, and a second clamping diode with cathode connected to the control input and anode connected to the output pin. These diodes act as mediators to limit voltage swings at the internal node, preventing excessive voltage drops that would otherwise delay the output driver's response to load transients.
2Productivity
If the NMOS output transistor gate voltage is allowed to swing freely, then the transistor can be fully enabled for high current supply, but large voltage swings cause delayed response and output transients
Solution Approach 1:
The clamping device modifies the voltage parameter at the control input of the output driver by limiting its swing range. Specifically, it prevents the control input voltage from dropping more than one diode drop below the output voltage. This parameter change ensures that when the load increases, the output driver can respond faster while still maintaining sufficient gate voltage to enable the NMOS transistor for high current supply.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The clamping diode significantly reduces the amplitude and duration of output load transients, improving load transient response and preventing voltage errors or system resets by maintaining the NMOS output transistor gate voltage close to the output voltage, thus enabling faster current supply.
Implementation Method 1
A clamping device is coupled between the output pin and an internal node of the regulator. The clamping device causes a voltage at a control input of the output driver to follow the voltage at the output pin when the output driver is disabled.
Implementation Method 2
Incorporating a clamping diode between the output pin and internal nodes of the LDO to limit the voltage drop, ensuring the NMOS output transistor gate voltage remains close to the output voltage
Data Source
AI summary
Apparatus and methods for reducing output load transients of a low dropout voltage regulator (“LDO”) are disclosed herein. A voltage regulator includes an output driver coupled to a regulator output pin, the output driver provides current to a load external to the regulator. A clamping device is coupled between the output pin and an internal node of the regulator. The clamping device forces a voltage at a control input of the output driver to follow the voltage at the output pin when the output driver is disabled.