LDO Regulator Compensation Circuit for Stable Phase Margin
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Solution Overview
Problem
Conventional low drop-out (LDO) linear regulators experience unstable operation due to the positioning of poles in the Bode diagram, particularly when frequency compensation using equivalent series resistance (ESR) is inadequate, leading to unstable phase margins and unreliable stability at varying load currents.
Innovation Solution
The integration of a buffer between the pass transistor and error amplifier, along with two compensation circuits that adjust the equivalent resistance of the output and gate nodes in inverse proportion to the load current, effectively shifting the poles' frequencies and maintaining a constant phase margin across load current changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frequency compensation is performed using ESR of the output capacitor, then the LHP zero position can be adjusted to improve stability, but the compensation becomes unreliable because ESR value cannot be accurately specified and varies with load conditions
Solution Approach 1:
The patent introduces an equivalent resistance component as an intermediary element connected to the output node of the error amplifier. This component serves as a mediator that provides predictable frequency compensation without relying on the uncertain ESR of the output capacitor. The equivalent resistance component creates a可控 (controllable) pole-zero configuration that improves stability reliability independent of load variations.
Solution Approach 2:
The patent changes the compensation approach from relying on ESR parameter (which varies and cannot be accurately specified) to using a dedicated equivalent resistance component with defined characteristics. By changing the compensation mechanism from ESR-based to equivalent resistance component-based, the system achieves reliable and predictable frequency compensation across varying load conditions.
2Reliability
If a large output capacitor is used to create a dominant pole for stable output voltage, then output stability improves, but the pole of the output node of the error amplifier moves closer to the dominant pole causing potential instability
Solution Approach 1:
The patent segments the frequency compensation function into two independent parts: the dominant pole created by the large output capacitor for output stability, and the equivalent resistance component creating a separate pole at the error amplifier output node. This segmentation allows each pole to be independently positioned and optimized, preventing the error amplifier pole from interfering with the dominant pole while maintaining both stability benefits.
Solution Approach 2:
The equivalent resistance component acts as an intermediary that decouples the interaction between the error amplifier output node and the dominant pole. By introducing this intermediate element, the patent creates a controlled pole configuration that prevents the error amplifier pole from moving too close to the dominant pole, thereby maintaining adequate phase margin while preserving output voltage stability.
3Device complexity
If the pole of the output node of the error amplifier is positioned close to the dominant pole to simplify circuit design, then circuit complexity reduces, but phase margin becomes small causing unstable operation
Solution Approach 1:
The equivalent resistance component serves as an intermediary that enables simple circuit design while maintaining reliable stability. By introducing this component, the patent creates a predictable pole configuration without requiring complex compensation networks. The intermediary element provides the necessary phase margin while keeping the overall circuit structure simple and easy to implement.
Data Source
AI summary
A low drop-out (LDO) linear regulator includes: a pass transistor coupled between an input terminal and an output terminal; an error amplifier suitable for amplifying and outputting a difference between a feedback voltage corresponding to an output voltage of the output terminal and a predetermined reference voltage; a buffer including an input terminal which is coupled to an output node of the error amplifier and an output terminal which is coupled to a gate of the pass transistor; a first compensation circuit suitable for driving an equivalent resistance of the output node of the error amplifier to be in inverse proportion to a load current; and a second compensation circuit suitable for driving an equivalent resistance of an output node of the buffer to be in inverse proportion to the load current.