Low Dropout Regulator Fast Mode Switching via Digital Timing Control

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Solution Overview

Problem

Conventional low dropout regulators have slower operation speeds due to the use of resistors and capacitors, leading to longer start-up times and increased power consumption in standby mode, making them unsuitable for high-frequency applications.

Innovation Solution

A low dropout regulator design incorporating an output-stage circuit, reference-voltage generation circuit, timing controller, and active low dropout circuit, utilizing digital enable signals to quickly generate and modulate output voltages, enabling faster response times and reduced power consumption in standby mode.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If conventional low dropout regulators use resistors and capacitors for frequency compensation, then the circuit stability is improved, but the operation speed deteriorates

Engineering Contradiction:
Improvecircuit stabilityVSAvoidoperation speed
Core Design Contradiction:
Stability of the object's compositionVSSpeed

Solution Approach 1:

The patent replaces the conventional resistor-capacitor frequency compensation mechanism with a digital control system that uses a timing controller and digital enable signals to regulate the output voltage. This substitution of analog passive components with a digital active control system eliminates the inherent speed limitations of RC circuits while maintaining stability through digital timing control.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the control parameter from analog voltage dividers to digital enable signals with specific timing characteristics. The timing controller generates enable signals with precisely controlled pulse widths and timing, allowing fast response without the bandwidth limitations imposed by RC compensation networks.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If conventional low dropout regulators use resistors and capacitors, then the circuit design is simplified, but the start-up time increases

Engineering Contradiction:
Improvecircuit design simplicityVSAvoidstart-up time
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The timing controller is pre-configured with timing parameters that determine the enable signal characteristics. When regulation is needed, the controller immediately generates the pre-programmed enable signal sequence, eliminating the gradual charging/discharging delays inherent in RC-based start-up sequences.

Inventive Principle:
Principle #10Preliminary action

3Use of energy by stationary object

If conventional low dropout regulators operate in standby mode, then the power consumption increases, but the response time to operation mode increases

Engineering Contradiction:
Improvestandby power consumptionVSAvoidmode switching time
Core Design Contradiction:
Use of energy by stationary objectVSLoss of time

Solution Approach 1:

The timing controller generates periodic enable signals with duty cycles optimized for different operating modes. In standby mode, the controller can generate minimal or zero-width enable pulses that consume negligible power while maintaining the ability to immediately transition to full operation mode when needed, eliminating the need for a separate standby power supply.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS9733655B2Low dropout regulators with fast response speed for mode switching
Publication Date: 2017.08.15 VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
  • US9733655B2 patent drawing
  • US9733655B2 patent drawing
  • US9733655B2 patent drawing

AI summary

A low dropout regulator is provided. The low dropout regulator includes an output-stage circuit, a reference-voltage generation circuit, a timing controller, and an active low dropout circuit. When the low dropout regulator is at an operation mode, the output-stage circuit is controlled by a first enable signal to generate first output voltage to an output node of the low dropout regulator. The reference-voltage generation circuit is controlled by a bias voltage to generate a first reference voltage. The timing controller is coupled to the output node and receives the first reference voltage. When the low dropout regulator is in the operation mode, the timing controller programs the first enable signal according to the reference voltage and the voltage at the output node. When the low dropout regulator is in a standby mode, the active low dropout circuit generates a second output voltage to the output node.