LDO Regulator Dual Error Amplifier High Load Current
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Solution Overview
Problem
Modern low dropout voltage regulators (LDOs) face challenges in supporting high load currents over a wide range of operating conditions with minimal additional circuitry.
Innovation Solution
The proposed solution involves generating first and second feedback signals, with a p-channel FET transistor and an n-channel FET transistor connected in series between the input voltage and ground, where the drain of the p-channel FET transistor is connected to the gate of a transistor, and the second amplifier output is connected to the gate of a p-channel FET transistor, allowing for efficient regulation of output voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDO design is used, then circuit simplicity is maintained, but the ability to support high load current is insufficient
Solution Approach 1:
The LDO regulator is divided into multiple functional blocks: a first error amplifier for voltage regulation, a second error amplifier for current regulation, and a pass transistor. This segmentation allows each block to be optimized for its specific function, enabling high load current support while keeping each individual block relatively simple.
Solution Approach 2:
The patent implements a dual-purpose error amplifier system where the first error amplifier handles voltage regulation and the second error amplifier handles current regulation. This multi-functionality allows the LDO to support high load currents across wide operating conditions without requiring entirely separate control circuits.
2Productivity
If additional circuitry is added to support high load current, then load current capability is improved, but circuit complexity increases
Solution Approach 1:
The patent merges voltage regulation and current regulation functions into a single integrated LDO circuit. The first and second error amplifiers work together within the same circuit architecture, sharing common components such as the reference voltage generator and feedback network. This merging achieves high load current capability without proportionally increasing overall circuit complexity.
Solution Approach 2:
The patent introduces an intermediary current sense amplifier that monitors the load current and provides feedback to the control circuit. This intermediary component enables precise current regulation without requiring complex direct control mechanisms, thus improving load current capability while adding minimal circuit complexity.
3Stability of the object's composition
If feedback control circuits are used for voltage regulation, then output voltage stability is improved, but the ability to handle wide operating conditions is limited
Solution Approach 1:
The patent employs dual feedback loops: one through the first error amplifier for voltage feedback and another through the second error amplifier for current feedback. These feedback mechanisms continuously monitor and adjust the output, maintaining stable voltage regulation across wide operating conditions including varying load currents and input voltages.
Solution Approach 2:
The LDO circuit uses dynamic error amplifiers that can adapt their operation based on operating conditions. The first and second error amplifiers work dynamically together, with their relative importance shifting based on whether the current demand is low or high, enabling stable regulation across a wide range of operating conditions.
Data Source
AI summary
A novel low dropout regulator (LDO) is presented. The LDO includes the generation of a first feedback signal and a second feedback signal. The first feedback signal and a reference signal connect to a first error amplifier. The second feedback signal and the first error amplifier output signal connect to a second error amplifier. The output signal from the second error amplifier is coupled to the gate of a FET transistor. The FET transistor can be either a p-channel FET transistor, an n-channel FET transistor, a NMOS pass transistor, or a PMOS pass transistor. The positive input terminal or the negative input terminal of the first amplifier or of the second amplifier therefore need to be configured accordingly. When the source of the FET transistor is connected to the input voltage VIN, the drain of the FET transistor is the output voltage VOUT; when the drain of the FET transistor is connected to the input voltage VIN, the source of the FET transistor is the VOUT.