LDO Pass Transistor Gate Circuit for PSR and Oscillation Stability

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Solution Overview

Problem

Low drop-out (LDO) regulators face challenges in minimizing power supply rejection (PSR) characteristics due to parasitic capacitance at the gate of the pass transistor, which can lead to deteriorated PSR characteristics and potential oscillations.

Innovation Solution

The implementation of a semiconductor circuit with a cascode connection circuit, mirror compensation capacitance, and an AC path capacitance between the input voltage node and the source of the NMOS transistor, which optimizes the PSR characteristics without shifting the power-supply conductance to the negative side.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If parasitic capacitance is added to the gate of the pass transistor, then the LDO regulator can be implemented, but the PSR characteristics deteriorate

Engineering Contradiction:
ImproveLDO regulator functionalityVSAvoidPSR characteristics
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces a capacitor connected between the gate of the pass transistor and a reference potential as an intermediary element. This capacitor acts as a mediator that filters high-frequency noise and parasitic capacitance effects at the gate, thereby improving PSR characteristics while maintaining the necessary LDO regulator functionality. The capacitor decouples the gate from high-frequency disturbances, allowing the LDO to function reliably without suffering from degraded PSR performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-affected harmful factors

If AC gain of gate signal is increased to improve PSR characteristics, then PSR performance improves, but power-supply conductance shifts to negative side causing oscillations

Engineering Contradiction:
ImprovePSR characteristicsVSAvoidoutput signal stability
Core Design Contradiction:
Object-affected harmful factorsVSStability of the object's composition

Solution Approach 1:

The patent modifies the electrical parameters of the gate circuit by introducing a capacitor with specific capacitance value. This parameter change adjusts the frequency response and AC gain characteristics of the gate signal without causing the power-supply conductance to shift to the negative side. The capacitor value is selected to optimize PSR characteristics while maintaining stable operation and preventing oscillations in the output signal.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively improves PSR characteristics by preventing oscillations and maintaining stable output voltage even when input voltage or load current fluctuations occur.

Implementation Method 1

a first capacitor connected between the second node and a fourth node of a first one of the plurality of second transistors

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

a second capacitor connected between the first node and the fourth node

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS12235665B2Semiconductor circuit and power supply device
Publication Date: 2025.02.25 KIOXIA CORP
  • US12235665B2 patent drawing
  • US12235665B2 patent drawing
  • US12235665B2 patent drawing

AI summary

A semiconductor circuit includes: a first transistor connected between a first node configured to input an input voltage and a second node configured to output an output voltage; a cascode connection circuit including a plurality of second transistors connected in a cascode configuration between the first node and a third node set at a first voltage; a first capacitor connected between the second node and a fourth node of a first one of the plurality of second transistors; and a second capacitor connected between the first node and the fourth node, wherein a fifth node of the first second transistor is connected to a gate of the first transistor.