LDO Regulator Negative Capacitance Compensation for High Frequency PSRR
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Solution Overview
Problem
Conventional low drop-out (LDO) regulators face challenges in maintaining a stable output voltage in high frequency ranges due to noise in the input power supply, which affects their power supply rejection ratio (PSRR), making it difficult to provide stable power to noise-sensitive electronic devices.
Innovation Solution
Incorporating a compensation circuit that generates negative capacitance associated with the gate node of the pass transistor, which helps to offset parasitic capacitance and improve the PSRR by ensuring the gate-source voltage remains constant, even with noisy input power supplies, thereby eliminating the need for large capacity output load capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDO regulators are used, then they provide stable power output with low noise, but they cannot maintain stable output voltage in high frequency ranges due to noise in input power supply
Solution Approach 1:
The patent introduces a compensation circuit as an intermediary component between the error amplifier and the pass transistor gate node. This compensation circuit includes a compensation capacitor and a negative impedance generator that work together to counteract the parasitic capacitance effects. The negative impedance generator produces a negative capacitance that cancels out the parasitic capacitance at the gate node, thereby improving PSRR in high frequency ranges without requiring changes to the core LDO regulator structure
Solution Approach 2:
The patent changes the electrical parameters at the gate node by introducing a negative capacitance through the compensation circuit. This parameter change effectively counteracts the parasitic capacitance that degrades PSRR at high frequencies. By adjusting the compensation capacitor value and the negative impedance generator parameters, the system optimizes the gate-node impedance characteristics to reject high frequency noise while maintaining stable output voltage
2Object-affected harmful factors
If large capacity output load capacitors are used to improve PSRR, then high frequency noise rejection improves, but the form factor of display driver ICs increases
Solution Approach 1:
The patent extracts the PSRR improvement function from the output load capacitor and relocates it to a compensation circuit at the gate node. Instead of relying on large output load capacitors to achieve high frequency noise rejection, the invention places a compensation capacitor and negative impedance generator at the gate node, where they directly counteract parasitic capacitance effects. This extraction allows for minimal or eliminated output load capacitors, significantly reducing the IC form factor while maintaining or improving PSRR performance
3Object-affected harmful factors
If noise blocking in high frequency range is made difficult, then input voltage noise passes through to output, but adding compensation circuits increases device complexity
Solution Approach 1:
The compensation circuit is designed to perform multiple functions within a single integrated structure. The negative impedance generator not only provides negative capacitance to counteract parasitic effects but also works in conjunction with the compensation capacitor to create a unified compensation mechanism. This multi-functional design achieves effective high frequency noise blocking without requiring separate complex compensation stages, thereby minimizing the increase in device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly enhances the PSRR of LDO regulators, particularly in high frequency ranges, ensuring stable output voltages and enabling a smaller form factor for display driver ICs by eliminating the requirement for large capacity output load capacitors.
Implementation Method 1
a compensation circuit configured to provide a negative capacitance to a gate node of the pass transistor
Data Source
AI summary
A low drop-out (LDO) regulator includes a pass transistor, a feedback circuit, an error amplifier, and a compensation unit. The pass transistor is configured to regulate a power supply and output an output voltage according to a control signal. The feedback circuit is configured to generate a feedback voltage based on the output voltage. The error amplifier is configured to output a comparison signal in response to a reference voltage and the feedback voltage. The compensation circuit is configured to generate a negative capacitance in association with a first node connected to a gate electrode of the pass transistor.