Low-Loop-Gain LDO Offset Correction for Stable Load Regulation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Low loop gain LDO regulator circuits face challenges in maintaining loop stability and achieving good load regulation, particularly at high frequencies, due to limitations in correcting errors caused by load variations.

Innovation Solution

Incorporating an offset error correction circuit that generates an opposing voltage as a function of load current to cancel out variations in the output voltage, using a sense FET to sense the load current and generate an offset current, which is then used to imbalance the input current to transistors, creating a voltage offset that reduces output voltage variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the loop gain of the LDO regulator is reduced, then the power conversion efficiency is improved, but the load regulation capability deteriorates

Engineering Contradiction:
Improvepower conversion efficiencyVSAvoidload regulation capability
Core Design Contradiction:
Loss of energyVSManufacturing precision

Solution Approach 1:

The error correction function is segmented into two independent paths: a main feedback path for overall voltage regulation and a separate offset correction path that specifically addresses load regulation errors. This segmentation allows the main loop to operate with low gain for efficiency while the correction path compensates for regulation deficiencies.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

An intermediary offset voltage signal is introduced to mediate between the low loop gain operation and the required load regulation performance. This offset voltage, generated by sensing load current and processing it through gain stages, acts as a corrective intermediary that compensates for the insufficient error correction capability of the low gain main loop.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Volume of moving object

If the switching frequency of the SMPS is increased, then the size of inductors is reduced, but the output ripple voltage frequency increases

Engineering Contradiction:
Improveinductor sizeVSAvoidoutput ripple voltage frequency
Core Design Contradiction:
Volume of moving objectVSSpeed

Solution Approach 1:

A feedback mechanism senses the load current and generates an offset correction signal that is injected into the error amplifier. This feedback loop dynamically compensates for the effects of high-frequency switching ripple on the output voltage, allowing the system to operate at high switching frequencies with reduced inductor size while maintaining clean output voltage.

Inventive Principle:
Principle #23Feedback

3Loss of energy

If the loop gain is low, then power conversion efficiency is improved, but the ability to correct errors caused by load variations deteriorates

Engineering Contradiction:
Improvepower conversion efficiencyVSAvoiderror correction capability
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The offset correction signal is generated in advance based on load current sensing, before the actual voltage error occurs. By preliminarily determining the required correction based on anticipated load variations, the system can proactively compensate for errors rather than reactively correcting them, maintaining reliability with low loop gain.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The conventional high-gain voltage feedback mechanism is supplemented by an alternative error correction mechanism that uses load current sensing and offset voltage injection. This substitutes part of the traditional voltage-based error correction with a current-based predictive correction approach, enabling low-gain operation without sacrificing error correction capability.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS11611316B2Load regulation for LDO with low loop gain
Publication Date: 2023.03.21 PSEMI CORP
  • US11611316B2 patent drawing
  • US11611316B2 patent drawing
  • US11611316B2 patent drawing

AI summary

Circuits and methods for maintaining loop stability and good load regulation in low loop gain LDO regulator circuits. Embodiments encompass LDO regulator circuits that include an offset error correction circuit that generates an opposing voltage VOFFSET as a function of load current to substantially cancel out variations in VOUT that would otherwise occur due to load regulation limitations of the LDO regulator circuits. Embodiments use VOFFSET to imbalance currents in differential paths in a last-stage LDO error-amplifier so that an offset is propagated to a pair of inputs to the error-amplifier, thereby altering the output voltage VOUT to a corrected value. Benefits include improved LDO load regulation even when feedback loop gain is low, the available of both digital and analog implementations, high LDO accuracy and less variation of the output voltage VOUT, and suitability for implementation in integrated circuits for applications such as high precision power supplies.