LDO Offset Error Correction for Low Loop Gain Load Regulation
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Solution Overview
Problem
Low loop gain LDO regulator circuits face challenges in maintaining loop stability and good load regulation, particularly when dealing with high frequency output ripple voltages and noise-sensitive circuitry.
Innovation Solution
Incorporating an offset error correction circuit that generates an opposing voltage as a function of load current to cancel out variations in the output voltage, using a sense FET and an offset current generator to balance input currents and create a voltage offset in the opposite direction of the uncorrected value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the feedback loop gain of the LDO regulator circuit is reduced, then the circuit complexity and power consumption are reduced, but the load regulation performance deteriorates
Solution Approach 1:
The invention segments the load regulation function into two parts: the main LDO regulator circuit with reduced loop gain, and a separate compensation circuit. This segmentation allows the main regulator to operate with lower complexity while the compensation circuit handles the precision load regulation, resolving the contradiction between circuit complexity and load regulation performance.
Solution Approach 2:
The compensation circuit acts as an intermediary that senses the output voltage and injects a compensating signal to correct load regulation errors. This intermediary mechanism enables the main LDO circuit to maintain simple architecture while achieving precise load regulation through the mediating compensation action.
2Use of energy by moving object
If the feedback loop gain is reduced, then the stability margin is reduced, but the power consumption and noise are reduced
Solution Approach 1:
The stability function is segmented between the main LDO regulator with reduced loop gain and the compensation circuit. The main regulator consumes less power and generates less noise due to lower loop gain, while the compensation circuit provides the additional stability margin needed, resolving the contradiction between power consumption and loop stability.
3Use of energy by moving object
If the LDO regulator is used with high frequency SMPS, then the power conversion efficiency is improved, but the output ripple voltage increases
Solution Approach 1:
The compensation circuit serves as an intermediary that filters and suppresses the high frequency ripple voltage generated by the SMPS. It senses the output voltage variations and injects compensating signals to cancel the ripple, enabling the system to operate at high switching frequencies while maintaining clean output suitable for noise-sensitive circuitry.
4Object-generated harmful factors
If the loop gain is reduced to lower noise, then the PSRR is reduced, but the power consumption is reduced
Solution Approach 1:
The noise suppression function and PSRR function are segmented between the main LDO regulator and the compensation circuit. The main regulator operates with low loop gain to minimize internal noise, while the compensation circuit provides the necessary PSRR to suppress power supply variations, resolving the contradiction between noise and PSRR.
Data Source
AI summary
Circuits and methods for maintaining loop stability and good load regulation in low loop gain LDO regulator circuits. Embodiments encompass LDO regulator circuits that include an offset error correction circuit that generates an opposing voltage VOFFSET as a function of load current to substantially cancel out variations in VOUT that would otherwise occur due to load regulation limitations of the LDO regulator circuits. Embodiments use VOFFSET to imbalance currents in differential paths in a last-stage LDO error-amplifier so that an offset is propagated to a pair of inputs to the error-amplifier, thereby altering the output voltage VOUT to a corrected value. Benefits include improved LDO load regulation even when feedback loop gain is low, the available of both digital and analog implementations, high LDO accuracy and less variation of the output voltage VOUT, and suitability for implementation in integrated circuits for applications such as high precision power supplies.