LDO Output Circuit with PMOS and Capacitor for Transient Response
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Solution Overview
Problem
Low-dropout voltage regulators struggle to respond quickly to variations in load current, leading to unstable output voltage, particularly in applications requiring fast response times such as digital logic circuits, where conventional solutions like large capacitors or NMOS transistors increase costs or pin count.
Innovation Solution
A circuit comprising a current source, two PMOS transistors, and a capacitor connected to the output of the LDO regulator, which diverts and compensates current to stabilize the output voltage by drawing predetermined amounts of current from the LDO output in response to sudden changes, reducing transient currents and voltage fluctuations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional LDO regulator design is used, then the circuit is simple and economical, but the response to load current variations is slow
Solution Approach 1:
The circuit pre-charges a capacitor during normal operation, storing energy in advance. When a load transient occurs, this pre-stored energy is immediately discharged to compensate for the voltage drop, providing fast response without requiring a complex control system. The first PMOS transistor and capacitor are configured to automatically discharge when voltage drops occur.
Solution Approach 2:
A capacitor is introduced as an intermediary energy storage element between the LDO output and the load. This capacitor, controlled by PMOS transistors, acts as a buffer that can rapidly supply or absorb current during transients, decoupling the slow LDO response from the fast load requirements.
2Speed
If large capacitors are added to improve response time, then the response to load variations improves, but the cost and pin count increase
Solution Approach 1:
Instead of using a single large capacitor, the invention uses a smaller capacitor combined with PMOS transistors that are activated locally only when needed. The transistors control the capacitor's connection to the output, providing large effective capacitance during transients while maintaining small physical capacitor size during normal operation.
Solution Approach 2:
The circuit dynamically switches the capacitor into and out of the circuit using PMOS transistors. During normal operation, the capacitor is disconnected or partially connected to minimize its effect. During transients, the transistors rapidly connect the capacitor to provide immediate current support, making the effective capacitance variable rather than fixed.
3Speed
If NMOS transistors with high threshold voltage are used, then the response time improves, but the cost increases
Solution Approach 1:
The invention changes the key parameter from transistor threshold voltage to transistor type and circuit configuration. By using PMOS transistors with appropriate sizing and biasing, the circuit achieves fast response through pre-charged capacitor discharge rather than relying on high-threshold NMOS transistors, thereby reducing manufacturing cost while maintaining performance.
Data Source
AI summary
An output circuit at the output of an LDO regulator has two FETs (Field-Effect Transistors), a current source and a capacitor. The first FET is connected to the LDO output and a second voltage supply. The second FET is connected in series with the current source between the LDO output and the second voltage supply. The second FET is connected to the first FET in such a matter that a bias voltage is supplied to the first FET so that in static conditions the first FET draws predetermined amounts of current from the LDO output and to divert the predetermined amounts of current to the LDO output or to draw additional amounts of current from the LDO output to compensate for transient currents on the LDO output and to reduce variations in the output voltage of the LDO regulator. The capacitor with the current source defines a time constant to control the recovery of the output circuit from sudden drops or rises in voltage at the LDO regulator output to allow the LDO regulator to respond without adverse effect to the LDO output voltage.