Multi-Stage LDO Regulator Power Sequencing with Gm Capacitor Control
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Solution Overview
Problem
Multi-stage low drop-out (LDO) regulators experience slow power up and power down times due to the presence of large decoupling capacitors, which are necessary for high Power Supply Rejection Ratio (PSRR) but hinder rapid voltage changes, making them unsuitable for noise-sensitive circuitry that requires fast power transitions.
Innovation Solution
Incorporating transconductance amplifiers (Gm amplifiers) to dynamically charge and discharge capacitors during power up and power down, allowing for rapid voltage changes independently of capacitor values and output impedance, thereby accelerating the power up and power down processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large decoupling capacitors are used in multi-stage LDO regulators, then Power Supply Rejection Ratio (PSRR) is improved, but power up and power down times increase
Solution Approach 1:
The patent applies preliminary action by pre-charging the decoupling capacitors through controlled current sources before the LDO regulator operates. During power-up, current sources are activated to charge the large decoupling capacitors in advance, and during power-down, current sources discharge them rapidly. This preliminary charging/discharging action resolves the contradiction by enabling fast power transitions while maintaining the large capacitor values needed for high PSRR.
2Stability of the object's composition
If large decoupling capacitors are used to filter noise, then output voltage stability is improved, but the ability to provide rapid voltage changes deteriorates
Solution Approach 1:
The patent applies dynamics by making the capacitor charging/discharging process controllable and dynamic rather than passive. Current sources with controllable magnitude are used to charge and discharge the decoupling capacitors at different rates depending on the operational phase. During normal operation, the capacitors provide stable filtering, but during power transitions, the current sources dynamically adjust to enable rapid voltage changes, thus resolving the contradiction between stability and speed.
3Reliability
If multi-stage LDO configuration is used, then Power Supply Rejection Ratio is improved, but circuit complexity increases
Solution Approach 1:
The patent applies universality by designing current sources that serve multiple functions: they charge decoupling capacitors during power-up, discharge them during power-down, and can operate in parallel with the LDO regulator's normal operation. This multi-functionality reduces the need for separate dedicated charging/discharging circuits, thereby mitigating the increase in circuit complexity while maintaining the benefits of multi-stage configuration for high PSRR.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of Gm amplifiers enables fast power up and power down times in multi-stage LDO regulators, ensuring that noise-sensitive circuitry receives stable power quickly and is powered down efficiently, meeting the demands of downstream circuitry for rapid power availability and absence.
Implementation Method 1
an input transconductance amplifier configured to charge and/or discharge the input capacitor to achieve a desired charge level within a specified time independently of the value of the input capacitor
Implementation Method 2
Incorporating transconductance amplifiers (Gm amplifiers) to dynamically charge and discharge capacitors during power up and power down
Data Source
AI summary
Circuits and methods that provide for fast power up and power down times in a multi-stage LDO regulator. In one embodiment, a multi-stage LDO regulator circuit includes, for each stage for which fast power up and/or power down times are desired, at least one transconductance amplifier coupled and configured to compare a primary reference voltage to one of a secondary reference voltage for the stage or an output voltage of the stage, and coupling and configuring the at least one transconductance amplifier to charge and/or discharge an associated capacitor to achieve a desired charge level within a specified time independently of the value of the associated capacitor. In general, the transconductance amplifiers of each stage are configured to charge and/or discharge an associated capacitor in synchronism with a voltage present on the primary reference voltage input.


