LDO Regulator PSRR Improvement via Bias Line Capacitance Reduction
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Solution Overview
Problem
Current linear voltage regulators face challenges in reducing parasitic capacitance effects on power supply rejection ratio (PSRR), leading to noise interference and impedance issues in long bias lines, which degrades the performance of power management semiconductor chips.
Innovation Solution
A low dropout (LDO) device with a p-channel MOSFET pull-up, an n-channel MOSFET switch, and a digital gate driven by a ripple-free, pre-regulated filtered power source, along with a regulated power supply and enabling switch, is used to minimize bias line parasitic capacitance and improve PSRR through design layout optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If bias current is reduced to extend battery life, then power consumption decreases, but bias lines become high impedance and noise influence increases
Solution Approach 1:
The patent applies preliminary action by providing a pre-regulated filtered power source that prepares a clean, stable voltage before it reaches the digital gate and bias generation circuitry. This pre-conditioning of the power supply prevents noise from entering the system through parasitic capacitance, allowing the bias current to be reduced without compromising noise immunity. The ripple-free power source is established in advance to support low-power operation.
2Area of stationary object
If long bias lines are used to distribute bias current, then coverage area increases, but parasitic capacitance increases and PSRR degrades
Solution Approach 1:
The patent introduces an intermediary solution by placing buffer circuits at strategic points along the bias lines. These buffers act as mediators that refresh and re-drive the bias signal, preventing the accumulation of noise and the detrimental effects of parasitic capacitance over long distances. This allows extensive coverage area without direct proportionate increase in parasitic capacitance impact.
Solution Approach 2:
The patent segments the long bias lines into multiple shorter sections by inserting buffer circuits at intermediate points. Each segment is driven independently, preventing the entire long line from acting as a single high-capacitance path. This segmentation breaks up the parasitic capacitance into manageable portions, maintaining PSRR performance across large coverage areas.
3Device complexity
If global current biasing is used to simplify bias distribution, then device complexity decreases, but PSRR performance deteriorates due to long routing lines
Solution Approach 1:
The patent applies dynamics by making the bias distribution system adaptive through enabling switches that can dynamically connect or disconnect bias paths based on operational requirements. This dynamic configuration allows the system to maintain simple global biasing architecture while selectively activating local buffering or alternative bias paths when PSRR performance is critical, resolving the contradiction between simplicity and performance.
Data Source
AI summary
An apparatus and method for a system with improved power supply rejection ratio (PSRR) over a wide frequency range. The improved PSRR is achieved by negating the influence of the parasitic capacitance associated with the bias lines and the introduction of a regulated power supply with embodiments associated with providing a ripple free and regulated supply. With reduction of parasitic capacitance, and providing an ENABLE switch by a pre-regulated supply, the degradation of the PSRR is achieved. The embodiments include both n-channel and p-channel MOSFETs implementations, and a positive and negative regulated power supply voltage. With the combined influence of the utilization of the VREG supply, and the lowering of battery-to-bias line capacitance using design layout and improved floor planning an improved PSRR over a wide frequency distribution is achieved.