LDO Regulator PSRR Improvement via Transistor Mode Balancing
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Solution Overview
Problem
Low dropout voltage regulators (LDOs) face challenges in maintaining high power supply rejection ratio (PSRR) during very low voltage drop conditions and suffer from imbalanced current mirror operation, leading to reduced performance.
Innovation Solution
The proposed LDO design includes a first amplifier, a current mirror, and a second amplifier to ensure balanced operation of PMOS and mirror PMOS transistors, maintaining high PSRR by keeping both in the same saturation or triode mode even during low voltage dropouts, using a voltage sampler and additional transistors to stabilize the circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the LDO operates with very low voltage dropout (VDD-VOUT ≤ 100 mV), then the dropout voltage is reduced, but the PSRR deteriorates due to transistor mode imbalance
Solution Approach 1:
The patent employs a feedback mechanism where the second amplifier monitors the drain voltages of both the output PMOS and mirror PMOS, and adjusts their gate voltages accordingly. This feedback loop ensures that both transistors remain in the same operational mode (both saturation or both triode) even during low dropout conditions, thereby maintaining high PSRR while allowing very low voltage dropout operation.
Solution Approach 2:
The patent dynamically changes the gate voltages of the PMOS and mirror PMOS transistors based on the operating conditions. The second amplifier adjusts these voltage parameters in real-time to maintain balanced operation modes. By changing the gate voltage parameters, the transistors can operate in triode mode during low dropout while maintaining mode balance, thus preserving PSRR performance.
2Reliability
If the output PMOS is sized larger to maintain saturation mode during low dropout, then the PSRR is improved, but the circuit area and power consumption increase
Solution Approach 1:
The patent transitions from a static transistor sizing approach to a dynamic control approach. Instead of fixing the PMOS size to maintain saturation mode, the system dynamically adjusts the gate voltages using the second amplifier. This allows the transistors to adapt their operating mode (saturation or triode) based on real-time conditions, eliminating the need for oversized transistors while maintaining PSRR performance.
Solution Approach 2:
The patent changes the control parameter from fixed transistor dimensions to dynamic gate voltages. By adjusting the gate voltage parameters through the second amplifier, the system can maintain proper current mirroring and PSRR performance without requiring larger transistor areas. This parameter change allows flexible adaptation to different operating conditions without increasing circuit area.
3Ease of operation
If the current mirror PMOS is kept in saturation mode while output PMOS enters triode mode during low dropout, then the current mirror function is maintained, but the PSRR deteriorates due to mode imbalance
Solution Approach 1:
The second amplifier serves as a feedback control device that monitors the drain voltages of both PMOS transistors and adjusts their gate voltages to maintain mode balance. This feedback ensures that when the output PMOS enters triode mode during low dropout, the mirror PMOS also transitions to triode mode, maintaining current mirror functionality while preserving PSRR through balanced operation.
Solution Approach 2:
The patent introduces asymmetry in the control approach while maintaining symmetry in the outcome. The second amplifier applies different gate voltage adjustments to each PMOS transistor based on their individual operating conditions, yet achieves symmetric mode operation (both saturation or both triode). This controlled asymmetry in voltage adjustment resolves the mode imbalance problem while maintaining current mirror function.
Data Source
AI summary
A low dropout voltage regulator (LDO) includes first and second amplifiers and a current mirror. The first amplifier includes a first input receiving a reference voltage and a second input receiving a voltage proportional to an output of the LDO. The current mirror includes an input current at a first end of the current mirror to an output current at a second end of the current mirror, the input current controlled by an output of the first amplifier and the output current being supplied to the output of the LDO. The second amplifier includes a first input coupled to the first end of the current mirror and a second input coupled to the second end of the current mirror.