LDO Regulator Weak Inversion MOSFET Gain Stage
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Solution Overview
Problem
Low power mode (LPM) electronic devices require LDOs that maintain regulated supply voltages with extremely low current consumption, but also need to handle varying load currents that can be orders of magnitude higher than in idle conditions, posing a challenge in achieving both low self-power consumption and high load current delivery.
Innovation Solution
An LDO regulator design featuring a bias current source and a gain stage with a MOS transistor biased in weak inversion, coupled with a current mirror, which increases load current by mirroring drain current and adjusts gate-source voltage in response to output voltage changes, allowing for low self-power consumption while delivering higher load currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the LDO regulator uses a conventional design with higher bias current to ensure stable operation, then the reliability and stability are improved, but the power consumption increases beyond the nanoampere range
Solution Approach 1:
The patent changes the operating parameters of the MOS transistor by biasing it in weak inversion mode instead of strong inversion, which dramatically reduces the bias current required while maintaining stability. This parameter change allows the LDO to operate with nanoampere-level current consumption while preserving regulatory stability through the exponential relationship between gate-source voltage and drain current in weak inversion.
Solution Approach 2:
The patent implements dynamic adjustment of the gate-source voltage of the first MOS transistor based on the output voltage level. When output voltage decreases, the gate-source voltage increases to boost load current capability. This dynamic operation allows the LDO to adapt its current consumption and drive capability according to actual load conditions, maintaining stability across varying operating points.
2Power
If the LDO regulator is designed to deliver high load currents, then the load driving capability is improved, but the self-power consumption increases significantly
Solution Approach 1:
The patent implements dynamic adjustment of the gate-source voltage of the first MOS transistor based on the output voltage level. When output voltage decreases, the gate-source voltage increases to boost load current capability. This dynamic operation allows the LDO to adapt its current consumption and drive capability according to actual load conditions, maintaining stability across varying operating points.
Solution Approach 2:
The feedback mechanism uses the output voltage level itself to control the gate-source voltage of the first MOS transistor, creating a self-regulating system. The LDO automatically adjusts its internal parameters based on its own output condition, eliminating the need for external control circuits that would consume additional power.
3Device complexity
If the LDO regulator uses a simple circuit topology, then the device complexity is reduced, but the dynamic range of load current is limited
Solution Approach 1:
The patent changes the operating parameters of the MOS transistor by biasing it in weak inversion mode instead of strong inversion, which dramatically reduces the bias current required while maintaining stability. This parameter change allows the LDO to operate with nanoampere-level current consumption while preserving regulatory stability through the exponential relationship between gate-source voltage and drain current in weak inversion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The LDO regulator achieves low self-power consumption (100 nA to 300 nA) while capable of delivering load currents up to several tens of microamperes, maintaining a large dynamic range and efficient current handling across varying load conditions.
Implementation Method 1
The gain stage includes a first MOS transistor biased in weak inversion. When the voltage at the output node (the secondary supply voltage) decreases the gate source voltage of the first MOS transistor increases because the first MOS transistor is biased in weak inversion
Implementation Method 2
A current mirror mirroring the drain current through the first MOS transistor to an output node. The drain current of the first MOS transistor is mirrored using the current mirror so that the current received at the output node is proportional to the bias current
Data Source
AI summary
An electronic device has an LDO regulator for varying loads. The LDO regulator includes a primary supply node coupled to a primary voltage supply. An output node provides a secondary supply voltage and a load current. A bias current source generates a bias current. A gain stage coupled to the bias current source increases the maximum available load current. The gain stage includes a first MOS transistor biased in weak inversion coupled to a current mirror which mirrors the drain current through the first MOS transistor to the output node. The gate-source voltage of the first MOS transistor increases in response to a decreasing secondary supply voltage level at the output node to increase the available load current.