LDO Regulator Parallel Path Transistor Compensation

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Conventional PMOS LDO voltage regulators face stability issues due to low phase margin and quiescent current challenges, especially with varying load conditions and output capacitance, leading to poor transient performance.

Innovation Solution

A low dropout (LDO) voltage regulator design incorporating a parallel path transistor and a fractional frequency response network, which includes MOS resistive elements and capacitors, is introduced to provide compensation and stabilize the feedback loop, ensuring stable operation across a wide range of load conditions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a voltage buffer is used to drive the P-channel pass transistor, then the pole associated with gate capacitance can be pushed beyond the unity-gain frequency, but the quiescent current increases significantly

Engineering Contradiction:

Improvephase marginVSAvoidquiescent current

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent extracts the buffering function from a dedicated voltage buffer circuit and relocates it to the error amplifier output stage. The error amplifier's output transistor directly drives the pass transistor gate, eliminating the need for a separate voltage buffer while maintaining the ability to push the gate capacitance pole beyond the unity-gain frequency.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The error amplifier is designed to perform multiple functions: error signal amplification, gate capacitance compensation, and direct driving of the pass transistor. This multi-functionality eliminates the need for separate compensation circuits and voltage buffers, reducing quiescent current while maintaining stability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If output capacitors with high ESR are used to create a compensation zero, then the pole-zero cancellation can be achieved, but the efficiency is reduced especially with low ESR ceramic capacitors

Engineering Contradiction:

Improvecompensation stabilityVSAvoidcompensation efficiency

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent replaces the passive ESR-based compensation mechanism with an active compensation circuit implemented in the error amplifier. Instead of relying on the resistive property of output capacitors, the circuit uses transconductance amplification and capacitive feedback to create the necessary zero in the transfer function, making compensation independent of output capacitor ESR.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Reliability

If a compensation zero is added within the LDO feedback loop, then pole-zero cancellation can be achieved, but the compensation is incomplete under certain conditions resulting in instability

Engineering Contradiction:

Improvepole-zero cancellationVSAvoidload condition adaptability

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The error amplifier's transconductance is designed to vary with the operating conditions, allowing the compensation zero to dynamically track the position of the dominant pole across different load conditions. This dynamic adaptation ensures complete pole-zero cancellation regardless of whether the LDO is operating under light or heavy load conditions.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent implements a feedback mechanism where the error amplifier monitors the output voltage and adjusts its output to maintain proper compensation. The feedback loop ensures that the compensation zero remains effective across varying load conditions by continuously adapting the error amplifier's transfer function.

Inventive Principle:

Principle #23Feedback

4Use of energy by moving object

If the LDO is designed for very low quiescent current, then battery life is extended, but the phase margin decreases under certain load conditions

Engineering Contradiction:

Improvequiescent currentVSAvoidphase margin

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The patent changes the operating parameters of the error amplifier to achieve high transconductance with minimal bias current. By optimizing the transistor sizing and biasing conditions, the circuit achieves sufficient gain and phase margin while maintaining very low quiescent current consumption, enabling battery-powered applications to achieve extended battery life without sacrificing stability.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS8115463B2Compensation of LDO regulator using parallel signal path with fractional frequency response

Publication Date: 2012.02.14 TEXAS INSTRUMENTS INC

AI summary

A low drop out (LDO) voltage regulator (10) includes a pass transistor (MPpass) having a source coupled by an output conductor (4) to a load and a drain coupled to an input voltage to be regulated. An error amplifier (2) has a first input coupled to a reference voltage, a second input connected to a feedback conductor (4A), and an output coupled to a gate of the pass transistor. A parallel path transistor (MPpa) has a source coupled to the input voltage, a gate coupled to the output (3) of the error amplifier (2), and a drain coupled to the feedback conductor. A feedback resistor (Rf) is coupled between the feedback conductor and the output conductor.