Self-Calibrating LDO Compensation for High-Frequency Resonance
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Solution Overview
Problem
High-frequency switched-mode power supplies (SMPS) cause resonance effects in low drop-out (LDO) regulator circuits, leading to feedback loop instability and reduced phase margin, which is detrimental for noise-sensitive circuitry.
Innovation Solution
Incorporating a second-order low pass filter (LPF) between the error amplifier and the driver FET, with an impedance-lowering device, and a programmable LPF with an oscillation detector and filter bit control circuit to dynamically adjust tuning values, effectively canceling resonance effects and maintaining system stability across varying capacitive load conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the LDO regulator circuit is designed to achieve high PSRR at high frequencies by increasing unity gain bandwidth, then the capability to suppress power supply variations is improved, but resonance effects cause feedback loop instability and degraded phase margin
Solution Approach 1:
The patent applies preliminary anti-action by introducing a lead compensator circuit that proactively provides phase lead to counteract the phase lag caused by resonance effects before they can destabilize the feedback loop. The compensator is designed with specific pole-zero placement to generate positive phase contribution at the resonant frequency, preemptively抵消ing the harmful phase degradation and maintaining loop stability throughout the frequency range.
2Stability of the object's composition
If a fixed compensation circuit is used to counteract resonance effects, then stability at specific operating conditions is improved, but adaptability to varying capacitive load conditions deteriorates
Solution Approach 1:
The patent implements dynamics by making the compensation circuit parameters adjustable through switchable capacitor banks and resistors that can be reconfigured based on detected load conditions. The system dynamically adapts the compensator's pole-zero locations and time constants to match different capacitive load scenarios, transforming a static compensation design into a flexible, condition-responsive system that maintains optimal phase margin across varying operating points.
Solution Approach 2:
The patent employs feedback mechanisms by incorporating sensors that monitor output voltage ripple, phase margin, and load conditions, which then feed back to control logic that adjusts the compensator parameters in real-time. This closed-loop adaptation ensures the lead compensator continuously optimizes its performance to counteract resonance effects under changing capacitive load conditions, maintaining stability without manual intervention.
3Volume of moving object
If switching frequency of SMPS is increased to scale down inductor size, then the size of power supply components is reduced, but high frequency output ripple voltage increases requiring higher PSRR
Solution Approach 1:
The patent introduces an intermediary lead compensator circuit positioned between the error amplifier and the feedback network that acts as a mediator to suppress high-frequency ripple voltage. The compensator's transfer function is specifically designed to provide attenuation at the SMPS switching frequency while maintaining DC gain for proper voltage regulation, effectively filtering harmful high-frequency components without requiring large external capacitors or inductors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures stable operation of LDO regulator circuits at high frequencies (above 1 MHz) by partially canceling resonance effects, maintaining positive phase margin, and accommodating a wide range of capacitive loads, thereby ensuring reliable power supply to noise-sensitive circuitry.
Implementation Method 1
oscillatory resonance effects. An LDO regulator circuit designed to achieve high PSRR at high frequencies is often designed to have a high unity gain bandwidth (UGB) at the highest frequencies (e.g., around 1 MHz). However, the Equivalent Series Resistance (ESR) and Equivalent Series Inductance (ESL) of load capacitances cause a resonance effect—that is, oscillations—at those high frequencies.
Implementation Method 2
Incorporating a second-order low pass filter (LPF) between the error amplifier and the driver FET
Data Source
AI summary
Low drop-out (LDO) regulator circuits and methods that can operate at high frequencies without the adverse consequences of an oscillatory resonance effect from a capacitive load. In a first embodiment, a low pass filter (LPF) is coupled to the LDO and tuned to cancel the oscillatory resonance effect. In a second embodiment, the LPF is a second-order LPF and/or programmable. Since the tuning values of the programmable LPF may be programmatically selected, a much greater range of external capacitors values (with attendant ESR and ESL values), as well as a wider range of system parasitic capacitances, can be accommodated while maintaining system stability. Some variants of the second embodiment include an oscillation detector and filter bit control circuit that allows the tuning values of the programmable LPF to be dynamically determined and re-determined. An impedance-lowering device may be coupled to lower the impedance of the connection to the LPF.