LDO/HDO Supplementary Current Source Bandwidth
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Solution Overview
Problem
Low drop-out voltage regulators face challenges with extended settling time and slow steady-state load dump recovery due to high frequency operations, which are exacerbated by the presence of a second closed feedback loop formed by Miller capacitance, leading to increased power consumption and silicon area requirements.
Innovation Solution
The introduction of a comparator and current source circuitry, which provides a supplementary current boost to assist the LDO/HDO in fast response during start-up and steady-state recovery, and the use of a shunting circuit to manage Miller capacitance compensation, thereby controlling the dominant pole and improving settling speed and bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If Miller capacitance compensation is used in the feedback control loop, then stability is improved and silicon area is reduced, but settling time increases and bandwidth is limited due to the dominant pole effect
Solution Approach 1:
The patent segments the compensation function into two parts: Miller capacitance for stability and a supplementary current source for fast transient response. The error amplifier handles steady-state stability while the supplementary current source activated by the comparator handles transient settling, allowing both stability and fast settling time without compromise.
Solution Approach 2:
The patent makes the supplementary current source dynamic by activating it only during transient conditions when the comparator detects voltage deviations. This dynamic activation allows the system to have fast settling time during transients while maintaining stable operation during steady-state, resolving the contradiction between stability and settling time.
2Reliability
If dominant pole compensation is used at the output of LDO to improve Power Supply Rejection Ratio (PSRR), then PSRR is improved over the entire frequency range, but power consumption increases and silicon area increases
Solution Approach 1:
The patent applies partial action by using only enough compensation to achieve the required PSRR performance. The Miller capacitance provides the necessary phase margin and PSRR improvement, while the supplementary current source is activated only partially during transient conditions, avoiding excessive power consumption and silicon area while maintaining adequate PSRR.
Solution Approach 2:
The patent prepares the system for PSRR improvement through preliminary Miller capacitance compensation, which establishes the baseline rejection ratio. The supplementary current source then provides additional transient response capability only when needed, achieving adequate PSRR without the excessive power and area costs of full dominant pole compensation.
3Speed
If the second closed loop formed by Miller capacitance is allowed to dominate at high frequencies, then bandwidth is increased, but settling time increases due to the slew rate of the error amplifier
Solution Approach 1:
The patent introduces a comparator as an intermediary element that detects voltage deviations and activates the supplementary current source. This intermediary mechanism allows the system to maintain the beneficial high-frequency bandwidth provided by the Miller capacitance while preventing the harmful settling time extension by providing additional current during transients to overcome the error amplifier's slew rate limitation.
Data Source
AI summary
An LDO/HDO circuit adds a supplementary current source to supply the output node. The current boosting section includes a digital comparator with a first input connected to the LDO's feedback loop and a second input connected to a reference level. The comparator then generates a digital output used to control the supplementary current source. This approach also can be used in a far-side implementation, where the local supply level for the load is boosted by the current source based a comparison of this local level and the output of the LDO. Miller capacitive compensation is also considered. Current in shunted to ground from a node in the Miller loop, where the level is controlled by the output of a digital comparator base on a comparison of the circuit's output voltage and a reference level.