LDO Transient Mitigation Using Dynamic RC and Adaptive Biasing
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Solution Overview
Problem
Low dropout regulators (LDOs) face a challenge in achieving a good transient response while minimizing quiescent current and circuit area, as smaller load capacitors and lower quiescent current can lead to degraded transient performance.
Innovation Solution
The proposed solution involves a voltage regulator circuit with a dynamic R-C network and adaptive biasing, which includes MOS-based resistors and capacitors, and a method that converts voltage drops into current signals to drive the output voltage terminal, increasing drive current and dynamically adjusting impedance to improve transient response.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a larger output capacitor is used to reduce transient output voltage drop, then transient response is improved, but circuit area and cost increase
Solution Approach 1:
The patent divides the transient response improvement function into two separate components: the output capacitor handles bulk energy storage, while a dedicated transient response circuit (comprising the second amplifier, third transistor, fourth transistor, and associated RC networks) handles rapid transient corrections. This segmentation allows each component to be optimized independently, achieving good transient response without requiring a large output capacitor.
Solution Approach 2:
The patent introduces an intermediary transient response circuit that acts as a mediator between the output voltage and the load. This circuit includes a second amplifier that detects output voltage changes and a third transistor that provides additional drive current during transients. The intermediary circuit compensates for voltage drops without requiring the output capacitor to be oversized.
2Loss of energy
If quiescent current is reduced to improve power efficiency, then power efficiency is improved, but transient response degrades
Solution Approach 1:
The patent implements preliminary action by maintaining a small standby current through the bias circuitry (first amplifier, second amplifier, and associated bias transistors) that is sufficient to detect voltage changes and initiate transient response, but low enough to maintain good power efficiency during idle periods. When a transient occurs, the circuit rapidly activates additional current paths.
Solution Approach 2:
The patent makes the quiescent current dynamic rather than static. The bias currents are controlled by voltage-dependent circuits that adjust the operating point based on load conditions. During normal operation, the quiescent current is minimized for power efficiency, but during transients, the circuit dynamically increases current delivery capability through the third transistor and associated current mirrors.
3Reliability
If the LDO is kept in peak operation to maintain fast transient response, then transient response is improved, but quiescent current increases
Solution Approach 1:
The patent implements self-service through voltage-dependent activation. The transient response circuit automatically activates when needed based on output voltage monitoring by the second amplifier, without requiring continuous peak operation. The circuit monitors its own output voltage and initiates transient correction only when voltage drops are detected, eliminating the need for continuous high-current standby operation.
Data Source
AI summary
Described embodiments include a voltage regulator circuit comprising an output voltage terminal configured to be coupled to a load that draws a load current, first and second amplifiers, and first, second, third, fourth and fifth transistors. The embodiment also includes a dynamic R-C network coupled between the third amplifier input and the seventh transistor current terminal, wherein the dynamic R-C network includes capacitors and MOS-based resistors, a third amplifier having a fourth amplifier input and a third amplifier output, wherein the fourth amplifier input is coupled to the output voltage terminal, and a capacitor that is coupled between the output voltage terminal and the fourth amplifier input.