LDPC Bit Interleaver Layout for 64-Symbol Burst Error Distribution
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems suffer from rapid performance degradation unless burst errors in digital broadcast channels are effectively distributed, requiring an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver optimized for an LDPC coder with a length of 16200 and code rate of 2/15, using 64-symbol mapping, which interleaves the LDPC codeword on a bit group basis with a parallel factor of 360, employing a specific permutation order to effectively distribute burst errors and improve error correction performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a bit interleaver is designed for BICM systems, then error correction performance is improved, but device complexity increases due to optimization requirements for modulation order and code parameters
Solution Approach 1:
The patent applies parameter changes by designing the bit interleaver with specific parameters optimized for 64-symbol mapping and LDPC codes with length 16200 and code rate 2/15. The interleaver uses a parallel factor of 360 and processes data in bit groups of 360 bits, with a specific permutation order (7, 11, 4, 38, 19, 25, 2, 43, 15, 26, 18, 14, 9, 29, 44, 32, 0, 5, 35, 10, 1, 12, 6, 36, 21, 33, 37, 34, 3, 31, 20, 16, 40, 23, 41, 22, 30, 39, 13, 24, 17, 42, 28, 8, 27) that achieves optimal error correction performance for these parameters without requiring complex adaptive designs.
2Reliability
If burst errors are distributed via bit-by-bit interleaver, then system robustness is improved, but the interleaver requires optimization for specific modulation order and code rate parameters
Solution Approach 1:
The patent applies segmentation by dividing the LDPC codeword into bit groups of 360 bits each (parallel factor), where each bit group corresponds to one modulation symbol in 64-symbol mapping. The interleaver permutes these bit groups according to a specific sequence, effectively distributing burst errors across different symbol positions. This segmented approach achieves robustness for 64-QAM modulation with LDPC(16200, 2/15) codes while maintaining a fixed design rather than requiring adaptation to different parameters.
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.