16200-Length LDPC Encoding for Co-Channel Interference Mitigation

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Solution Overview

Problem

Current terrestrial TV broadcasting systems face significant co-channel interference issues, leading to inefficient spectrum reuse due to the creation of white spaces, which hampers reception robustness and spectrum efficiency.

Innovation Solution

A new Low Density Parity Check (LDPC) code with a codeword length of 16200 and a code rate of 2/15 is developed, utilizing a specific LDPC encoding technique that efficiently performs encoding using a sequence derived from a parity check matrix, allowing for efficient transmission and reception of signals in overlapping areas with co-channel interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional terrestrial TV broadcasting is used, then transmission can be performed, but co-channel interference occurs and white spaces are created, deteriorating spectrum efficiency

Engineering Contradiction:
Improvereception robustnessVSAvoidspectrum efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies parameter changes by optimizing the LDPC code with specific parameters (code length of 16200 and code rate of 2/15) to achieve both reception robustness and spectrum efficiency. The modified parity check matrix with specific circulant permutation matrix configurations enables the system to maintain reliable reception while improving spectrum reuse capability in single frequency networks

Inventive Principle:
Principle #35Parameter changes

2Productivity

If frequency reuse is attempted in overlapping areas, then spectrum efficiency improves, but co-channel interference makes signal demodulation difficult

Engineering Contradiction:
Improvespectrum efficiencyVSAvoidsignal demodulation reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent changes the parameters of the LDPC code (code rate of 2/15 and length of 16200) to optimize performance in co-channel interference environments. The specific configuration of the parity check matrix with dual diagonal and identity matrix structures enables reliable signal demodulation even when frequency reuse is implemented in overlapping transmission areas

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If LDPC encoding is performed with standard configurations, then encoding can be completed, but encoding efficiency is insufficient for cloud transmission requirements

Engineering Contradiction:
Improveencoding implementationVSAvoidencoding efficiency
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The patent segments the parity check matrix into specific structures including dual diagonal matrices and identity matrices, organized in a systematic way that improves encoding efficiency. The codeword is divided into systematic parts and parity parts with specific lengths (2160 for systematic, 3240 for first parity, 10800 for second parity), enabling efficient processing while maintaining implementation feasibility

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent modifies the LDPC encoding parameters to match cloud transmission requirements, using a code rate of 2/15 and code length of 16200, with a parity check matrix configured with specific circulant permutation matrix sizes (360) to optimize encoding efficiency for the intended application

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9489259B2Low density parity check encoder having length of 16200 and code rate of 2/15, and low density parity check encoding method using the same
Publication Date: 2016.11.08 ELECTRONICS & TELECOMM RES INST
  • US9489259B2 patent drawing
  • US9489259B2 patent drawing
  • US9489259B2 patent drawing

AI summary

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).