LDPC Bit Interleaver Layout for 16-Symbol Burst Error Spreading
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver optimized for an LDPC coder with a length of 16200 and code rate of 3/15, using 16-symbol mapping, is designed to effectively distribute burst errors by interleaving the LDPC codeword on a bit group basis, with a specific permutation order, and integrated into a BICM device for next-generation broadcasting systems like ATSC 3.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors in the channel cause rapid performance degradation
Solution Approach 1:
The patent divides the LDPC codeword into multiple bit groups (45 groups of 360 bits each) and applies permutation interleaving at the bit group level. This segmentation approach distributes burst errors across different bit groups, preventing concentrated error patterns from overwhelming the decoding process, thereby improving system reliability without requiring complex interleaver structures
Solution Approach 2:
The patent optimizes the interleaver design by specifically tailoring the permutation order to match the LDPC code parameters (length 16200, code rate 3/15) and modulation scheme (16-symbol QAM). This parameter-specific optimization ensures maximum error distribution effectiveness for the given system configuration, achieving high reliability without unnecessary complexity
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then error distribution effectiveness improves, but the system loses flexibility
Solution Approach 1:
The patent employs a parameterized permutation interleaver design where the interleaving pattern is explicitly defined based on LDPC codeword length, code rate, and modulation order. This allows the same interleaver structure to be adapted to different system configurations by adjusting the permutation parameters, maintaining both optimization effectiveness and system flexibility
Solution Approach 2:
The interleaver design serves multiple functions: it distributes burst errors for the specific 16200-length LDPC code with 3/15 rate, accommodates 16-symbol QAM modulation, and can be extended to other code rates and modulation orders through parameter adjustment. This multi-functionality resolves the contradiction between optimization and adaptability
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.