LDPC Group-Wise Interleaving With 360-Bit Blocks for Error Floor Control
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Solution Overview
Problem
Current data transmission using LDPC codes faces challenges in maintaining excellent communication quality, particularly in ensuring error correction and minimizing the error floor phenomenon in decoding characteristics.
Innovation Solution
A data processing device and method that performs LDPC coding with a specific parity check matrix, group-wise interleaving, and mapping into signal points to enhance communication quality, utilizing a coding rate of 9/15 and 11/15, and includes a deinterleaving process to restore the original sequence of the LDPC code.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDPC coding is used with conventional parameters, then data transmission is achieved, but communication quality and error correction capability are insufficient
Solution Approach 1:
The patent applies parameter changes by modifying the LDPC code parameters to a code length of 64800 bits and coding rate of 9/15, and by defining a specific group-wise interleaving pattern with 360-bit groups. These parameter optimizations improve error correction capability and communication quality while maintaining manageable system complexity through standardized configurations.
Solution Approach 2:
The patent implements segmentation by dividing the LDPC code into bit groups of 360 bits for group-wise interleaving. This segmentation approach improves error floor characteristics by ensuring that error-prone regions are distributed across different groups, preventing concentrated errors from overwhelming the decoding process.
2Reliability
If group-wise interleaving is applied, then error floor phenomenon is reduced, but processing complexity increases
Solution Approach 1:
The patent optimizes the interleaving processing complexity by establishing a regular interleaving pattern with fixed parameters: 360-bit group size and a predetermined permutation sequence. This regular structure allows for efficient implementation using lookup tables or simple arithmetic operations, reducing processing complexity while maintaining improved error floor characteristics.
3Reliability
If code length is increased to improve error correction, then performance near Shannon limit is achieved, but transmission time increases
Solution Approach 1:
The patent achieves performance near the Shannon limit by selecting a code length of 64800 bits, which provides sufficient error correction capability for challenging channel conditions. The associated coding rate of 9/15 is optimized to balance redundancy for error correction with efficient use of transmission resources, minimizing unnecessary transmission time while achieving near-Shannon-limit performance.
Solution Approach 2:
The patent applies preliminary action through the group-wise interleaving process, which rearranges bits before transmission to preemptively protect against error patterns. This preliminary rearrangement ensures that even with longer code length, the effective transmission time is optimized by preventing error propagation and reducing the need for retransmissions.
Data Source
AI summary
The present technology relates to a data processing device and a data processing method capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code having a code length N of 64800 bits and a coding rate r of 9/15, 11/15, or 13/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of LDPC codes after the group-wise interleave is returned to an original sequence. The present technology, for example, can be applied to a case where data transmission using an LDPC code or the like is performed.