64800-Bit LDPC Encoder Structure for Co-Channel Interference

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current terrestrial TV broadcasting systems face co-channel interference issues, leading to white spaces where frequency reuse is not possible, resulting in deteriorated spectrum efficiency, and existing LDPC codes are not optimized for the DVB broadcast standard or specific LDPC encoding methods.

Innovation Solution

A new LDPC code with a length of 64800 and a code rate of 2/15 is developed, utilizing a specific LDPC encoding technique that includes a systematic part, a dual diagonal matrix, and an identity matrix, with a sequence representing the parity check matrix, allowing efficient encoding and decoding over wireless channels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If terrestrial TV broadcasting uses conventional frequency allocation, then co-channel interference is avoided, but spectrum efficiency deteriorates due to white spaces where frequency cannot be reused

Engineering Contradiction:
Improvereception robustnessVSAvoidspectrum efficiency
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies parameter changes by optimizing the LDPC code rate from conventional values to 2/15, and by designing a specific parity check matrix structure with 64800-bit block length. These parameter modifications enable the system to achieve both frequency reuse capability (improving spectrum efficiency) and reception robustness (maintaining reliability) in cloud transmission environments

Inventive Principle:
Principle #35Parameter changes

2Reliability

If LDPC code length is changed to optimize performance, then error correction capability improves, but compatibility with existing broadcast standards deteriorates

Engineering Contradiction:
Improveerror correction capabilityVSAvoidcompatibility with broadcast standards
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent applies local quality by designing a specific LDPC code structure with 64800-bit block length and 2/15 code rate that is optimized for cloud transmission while maintaining compatibility with DVB broadcast standards. The parity check matrix is specifically structured to provide enhanced error correction capability in overlapping signal regions without requiring complete departure from existing standard frameworks

Inventive Principle:
Principle #3Local quality

3Loss of energy

If cloud transmission technology is implemented to enable frequency reuse, then spectrum efficiency improves, but co-channel interference and synchronization issues worsen

Engineering Contradiction:
Improvespectrum efficiencyVSAvoidco-channel interference
Core Design Contradiction:
Loss of energyVSObject-affected harmful factors

Solution Approach 1:

The patent applies beforehand cushioning by using LDPC encoding with a specifically designed parity check matrix structure that provides error correction capability in advance. This preprocessing protects the transmitted signal against co-channel interference and synchronization issues that will occur in cloud transmission environments, enabling frequency reuse while mitigating harmful effects

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS10903856B2Low density parity check encoder having length of 64800 and code rate of 2/15, and low density parity check encoding method using the same
Publication Date: 2021.01.26 ELECTRONICS & TELECOMM RES INST
  • US10903856B2 patent drawing
  • US10903856B2 patent drawing
  • US10903856B2 patent drawing

AI summary

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).