64800-Length LDPC Encoding for Frequency Reuse Robustness

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Solution Overview

Problem

Current terrestrial TV broadcasting systems face co-channel interference issues, leading to white spaces and reduced spectrum efficiency, particularly in areas where frequency reuse is limited due to interference and synchronization challenges in overlapping signal areas.

Innovation Solution

A new Low Density Parity Check (LDPC) code with a length of 64800 and code rate of 2/15 is developed, utilizing an LDPC encoder and decoder that efficiently perform encoding and decoding using a specific sequence corresponding to a parity check matrix, enabling robust frequency reuse by mitigating co-channel interference through systematic and parity part management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If terrestrial TV broadcasting uses conventional frequency allocation, then service coverage is provided, but co-channel interference occurs and spectrum efficiency deteriorates due to white spaces

Engineering Contradiction:
Improveservice coverageVSAvoidspectrum efficiency
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies parameter changes by modifying the LDPC code parameters (code length N=64800, code rate 2/15, memory size 1800) to optimize error correction performance. This enables more robust signal reception that can tolerate co-channel interference, allowing frequency reuse and eliminating white spaces while maintaining service coverage

Inventive Principle:
Principle #35Parameter changes

2Loss of energy

If frequency reuse is implemented to improve spectrum efficiency, then spectrum efficiency improves, but co-channel interference increases and reception robustness deteriorates

Engineering Contradiction:
Improvespectrum efficiencyVSAvoidreception robustness
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The patent uses a composite coding structure combining systematic bits and parity bits in a specific arrangement (first parity part with 1800 bits, second parity part with 54360 bits). This composite structure provides enhanced error correction capability that maintains reception robustness even when frequency reuse increases co-channel interference

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The optimized LDPC code parameters (particularly code rate 2/15 and memory size 1800) provide stronger error correction performance, enabling the system to maintain reception robustness in the presence of co-channel interference from frequency reuse operations

Inventive Principle:
Principle #35Parameter changes

3Productivity

If LDPC encoding uses traditional methods, then encoding can be performed, but encoding efficiency is insufficient for the required code length and rate

Engineering Contradiction:
Improveencoding efficiencyVSAvoidcode generation accuracy
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent segments the encoding process into distinct stages: information bit input, systematic part generation, first parity part generation (1800 bits), and second parity part generation (54360 bits). This segmentation enables efficient processing while maintaining precise code generation according to the specified LDPC parameters

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a specific intermediate structure with memory size 1800 that serves as a mediator between the information bits and the final codeword. This intermediate structure facilitates efficient encoding operations while ensuring the final code meets the required length and rate specifications

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10425105B2Low density parity check encoder having length of 64800 and code rate of 2/15, and low density parity check encoding method using the same
Publication Date: 2019.09.24 ELECTRONICS & TELECOMM RES INST
  • US10425105B2 patent drawing
  • US10425105B2 patent drawing
  • US10425105B2 patent drawing

AI summary

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).