Flash Memory Controller LDPC Selection for Bad-Column Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Flash memory controllers face challenges in maintaining the correction ability and reliability of LDPC codes due to innate and run-time bad columns, which can coincide with the weaknesses of LDPC codes, leading to decreased performance.
Innovation Solution
A flash memory controller that calculates correlations between innate bad-column information and preset LDPC codes to select the LDPC code with the lowest correlation, and uses this selected code for decoding read information, thereby reducing the influence of bad columns on correction ability and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bad columns are skipped by reducing page size, then reliability is improved, but device complexity increases and correction ability decreases
Solution Approach 1:
The patent pre-calculates and stores the correlation between innate bad-column information and trapping sets of multiple preset LDPC codes before actual operation. During runtime, the controller simply queries this pre-computed data to select the most suitable LDPC code, avoiding complex real-time calculations and reducing processing complexity while maintaining high correction ability
Solution Approach 2:
The patent changes the parameter of LDPC code selection by introducing a correlation-based selection mechanism. Instead of using a fixed LDPC code or简单地 skipping bad columns, the system dynamically selects from multiple preset LDPC codes based on their correlation with bad columns, optimizing both correction ability and processing efficiency
2Reliability
If bad columns are skipped by reducing page size, then reliability is improved, but LDPC code correction ability decreases
Solution Approach 1:
The system pre-calculates the correlation between bad columns and trapping sets for multiple LDPC codes and stores this information in advance. This allows the controller to make informed decisions about which LDPC code to use without performing complex real-time analysis, thereby maintaining high correction ability while improving reliability
Solution Approach 2:
The patent optimizes the LDPC code parameters by selecting from multiple preset codes with different characteristics. By choosing the code with lowest correlation to bad columns, the system maximizes correction ability while ensuring reliability, avoiding the need to reduce page size
Data Source
AI summary
A flash memory controller used to access a flash memory includes a read-only memory, a processor, and an error correction code unit. The read-only memory is used to store a code. The processor executes the code to control access to the flash memory. The error correction code unit includes a control module and a decoder. The control module respectively calculates a first correlation between innate bad-column information which records the location of innate bad columns that become damaged after the read-only memory being manufactured and a plurality of trapping sets of a plurality of preset LDPC (low-density parity check) codes and uses the preset LDPC code which has the lowest first correlation as a selected LDPC code. The decoder decodes read information obtained from the flash memory according to the selected LDPC code.