QC-LDPC Decoder Memory Bank Reordering for Parallel Decoding
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Solution Overview
Problem
LDPC decoders face limitations in maximizing parallel decoding operations due to hardware resource constraints, which affect the number of cycles required to process layers of quasi-cyclic LDPC codes, especially when columns of the codeword are not optimally assigned to memory banks.
Innovation Solution
The proposed solution involves a decoder circuit with reordering stages that rearrange the columns of the codeword based on the number of memory banks and the participation of columns in decoding, creating an extended base matrix to equalize column distribution across memory banks, thereby maximizing parallel decoding operations without increasing memory requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If columns of the codeword are assigned to memory banks in a simple sequential order, then the memory bank assignment is straightforward and simple, but the distribution of columns participating in decoding is uneven across memory banks, reducing parallel decoding efficiency
Solution Approach 1:
The patent applies preliminary action by reordering the columns of the codeword before storing them in memory banks. The reordering stage rearranges columns based on their participation in decoding operations, ensuring that columns requiring parallel processing are distributed across different memory banks in advance. This preliminary reorganization enables the memory banks to operate in parallel more efficiently during the decoding process, resolving the contradiction between simple assignment and decoding efficiency.
2Productivity
If the number of parallel decoding operations is increased to improve throughput, then decoding speed increases, but the hardware resources required increase proportionally
Solution Approach 1:
The patent applies segmentation by dividing the decoding process into multiple stages: a reordering stage that prepares the codeword, a memory storage stage that distributes data, and a decoding stage that processes information. By segmenting the columns into different memory banks based on their decoding participation patterns, the system can process multiple columns in parallel using the same hardware resources, thereby increasing throughput without proportionally increasing hardware complexity.
3Loss of time
If the codeword is stored in memory banks without reordering, then the memory access pattern is simple and fast, but the number of cycles required to complete a layer of decoding increases due to uneven column distribution
Solution Approach 1:
The reordering stage performs preliminary action by reorganizing the codeword columns before they are stored in memory banks. This reordering ensures that columns participating in the same decoding operations are distributed across different memory banks, allowing for more efficient parallel access during decoding. The one-time reordering operation reduces the total number of decoding cycles required, compensating for the additional complexity introduced by the reordering stage.
Data Source
AI summary
A decoder circuit includes an input to receive a first codeword encoded based on a quasi-cyclic low-density parity-check (QC LDPC) code and a plurality of memory banks to store the received codeword. Each column of the received codeword is assigned to one of the plurality of memory banks based at least in part on an order of the plurality of columns in the received codeword. A first reordering stage is to change the memory bank assignment for one or more of the plurality of columns by reordering the columns in the received codeword. An LDPC decoder is to decode the reordered codeword stored in the plurality of memory banks based at least in part on the QC LDPC code. A second reordering stage is to output the decoded codeword from the plurality of memory banks based at least in part on an order of the columns in the first codeword.