LDPC Base Graph Selection for 5G NR CRC Overhead Reduction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current 5G NR networks face inefficiencies in channel coding, particularly in CRC attachment and modulation and coding scheme (MCS) table optimization, due to the use of two LDPC base graphs, which can lead to increased CRC overhead and complexity in error detection and spectral efficiency.

Innovation Solution

An apparatus and method that generate code blocks with parity bits using cyclic redundancy checks, determining the number of parity bits based on an applied linear error correcting code base graph and information bits, and encoding using either of two LDPC base graphs, with a nested MCS table structure to optimize channel performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If two LDPC base graphs are used for channel coding in 5G NR, then coding flexibility and performance optimization are improved, but CRC overhead increases and system complexity increases

Engineering Contradiction:
Improvechannel coding performanceVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent dynamically changes parameters including the number of CRC bits (16 or 24 bits), selection of LDPC base graph (BG1 or BG2), and code rate based on transport block size. This allows optimization of coding performance for different data sizes while managing complexity through conditional parameter selection rather than fixed configurations

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent segments the coding space into different regions based on transport block size thresholds. For TB ≤ 3840 bits, BG2 is used with specific CRC lengths; for TB > 3840 bits, BG1 is used. This segmentation allows each base graph to be optimized for its appropriate size range, improving overall reliability while managing complexity through clear division of operations

Inventive Principle:
Principle #1Segmentation

2Productivity

If CRC overhead is reduced for smaller transport blocks, then spectral efficiency is improved, but error detection capability may be compromised

Engineering Contradiction:
Improvespectral efficiencyVSAvoiderror detection capability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent changes the CRC bit length parameter based on transport block size: 16 bits for smaller blocks (TB ≤ 3840) and 24 bits for larger blocks (TB > 3840). This dynamic parameter adjustment optimizes spectral efficiency for small packets while maintaining adequate error detection for larger packets that require stronger protection

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

Different CRC overhead levels are applied locally to different transport block size ranges. Smaller blocks receive 16-bit CRC for efficiency, while larger blocks receive 24-bit CRC for enhanced error detection. This local differentiation allows spectral efficiency improvement where possible without compromising overall error detection capability

Inventive Principle:
Principle #3Local quality

3Device complexity

If a single LDPC base graph is used, then device complexity is reduced, but coding performance optimization for different transport block sizes is limited

Engineering Contradiction:
Improveimplementation complexityVSAvoidcoding performance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent implements a universal LDPC coding system that can function with either single or dual base graphs depending on configuration. The system universally supports both BG1 and BG2 with appropriate selection based on transport block size, allowing flexible deployment scenarios while maintaining optimized performance through conditional multi-functionality

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11070314B2Use of LDPC base graphs for NR
Publication Date: 2021.07.20 NOKIA SOLUTIONS & NETWORKS OY
  • US11070314B2 patent drawing
  • US11070314B2 patent drawing
  • US11070314B2 patent drawing

AI summary

An apparatus is provided which comprises at least one processor, at least one memory including computer program code, and the at least one processor, with the at least one memory and the computer program code, being arranged to cause the apparatus to at least perform generating a code block including information bits and parity bits, the parity bits being generated by performing a cyclic redundancy check on the information bits, determining the number of parity bits used in generating the code block based on an applied linear error correcting code base graph and/or based on the number of the information bits, and encoding the code block by using the applied linear error correcting code base graph.