LDPC Base Graph and Interleaver Design for High-Order Modulation

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Solution Overview

Problem

Current wireless communication systems face challenges in supporting high-order modulation schemes due to incompatibility of base graphs with complex LDPC codes, leading to increased overhead and poor error floor performance, which results in decreased reliability and throughput.

Innovation Solution

The implementation of a base graph design that supports second-degree variable nodes for higher significance bits, with a universal base graph applicable to both uniform and probabilistic shaping, and the use of interleavers to map lifted graphs to symbols, allowing for efficient joint LDPC coding and modulation operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If base graphs are designed to support high-order modulation schemes, then channel reliability and throughput are improved, but base graph complexity and incompatibility with complex LDPC codes increase

Engineering Contradiction:
Improvechannel reliabilityVSAvoidbase graph complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The base graph is segmented into an information set and a parity set, with the information set further divided into multiple information subsets. This segmentation allows different portions of the code to be optimized for different functions, enabling support for high-order modulation while managing complexity through structured organization of code elements.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different base graph designs are applied to different significance levels of information bits. Specifically, first information nodes (higher significance) use base graphs with second-degree variable nodes, while second information nodes (lower significance) use base graphs with third-degree variable nodes. This local differentiation optimizes performance for each bit significance level without requiring the entire system to handle maximum complexity.

Inventive Principle:
Principle #3Local quality

2Productivity

If base graphs are designed to support high-order modulation schemes, then throughput is improved, but overhead increases

Engineering Contradiction:
ImprovethroughputVSAvoidoverhead
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The system dynamically selects different base graph configurations based on the modulation order being used. For higher-order modulations, base graphs with second-degree variable nodes are employed to maximize throughput, while for lower-order modulations, base graphs with third-degree variable nodes are used. This dynamic adaptation allows the system to optimize throughput for each modulation scheme without incurring unnecessary overhead from universally complex base graphs.

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If base graphs are designed to support high-order modulation schemes, then compatibility with modulation schemes is improved, but error floor performance deteriorates

Engineering Contradiction:
Improvecompatibility with modulation schemesVSAvoiderror floor performance
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

Different base graph designs are applied to different significance levels of information bits. Specifically, first information nodes (higher significance) use base graphs with second-degree variable nodes, while second information nodes (lower significance) use base graphs with third-degree variable nodes. This local differentiation optimizes performance for each bit significance level without requiring the entire system to handle maximum complexity.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent applies second-degree variable nodes only to the first information nodes (higher significance bits) rather than uniformly across all information nodes. This partial application provides sufficient compatibility with high-order modulation schemes for the most critical bits while avoiding the error floor performance deterioration that would result from applying complex base graphs uniformly to all bits.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20240406797A1Joint low-density parity-check coding and modulation designs
Publication Date: 2024.12.05 QUALCOMM INC
  • US20240406797A1 patent drawing
  • US20240406797A1 patent drawing
  • US20240406797A1 patent drawing

AI summary

Methods, systems, and devices for wireless communications are described herein. A transmitting device (e.g., a user equipment (UE), a network entity) may generate a low-density parity-check code according to a base graph, which may be defined by variable nodes and check nodes. The base graph may support second degree variable nodes in the information nodes of the base graph and a larger quantity of second degree nodes associated with higher significance bits than with lower significance bits. Higher significance levels (e.g., bits) may correspond to higher channel reliabilities. The base graph may be a universal base graph or may include additional rules specific to probabilistic shaping. In some examples, an interleaver may be defined to map the base graph to symbols. In some cases, the UE may report its capability to support one or more interleavers, or the network entity may configure the UE with an interleaver.