LDPC Base Matrix Selection for Error Floor and Decoding Throughput

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Solution Overview

Problem

Current LDPC codes face challenges such as error floor and limited decoding throughput, which hinder their use in ultra-high reliability transmission and limit the maximum parallelism in hierarchical decoding.

Innovation Solution

The proposed method involves using a base matrix for LDPC coding and decoding that includes elements indicating an all-zero square matrix and a cyclic shift of an identity matrix, with subsets of base matrices having the same coding rate, to improve error floor performance and decoding speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If conventional LDPC codes are used, then decoding complexity is reduced, but error floor performance deteriorates and reliability is limited

Engineering Contradiction:
Improvedecoding complexityVSAvoiderror floor performance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent applies parameter changes by modifying the base matrix structure to include cyclic shift elements and organizing base matrices into subsets with different coding rates. This transforms the conventional LDPC code parameters to achieve better error floor performance while maintaining decoding complexity through the sparse structure.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent segments the base matrix into multiple subsets where each subset contains base matrices with the same coding rate. This segmentation allows the system to select appropriate subsets for different transmission conditions, improving reliability without significantly increasing overall decoding complexity.

Inventive Principle:
Principle #1Segmentation

2Productivity

If maximum parallelism is adopted in hierarchical decoding, then decoding throughput is increased, but error floor performance deteriorates

Engineering Contradiction:
Improvedecoding throughputVSAvoiderror floor performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces dynamics by allowing the selection of different base matrix subsets based on transmission conditions. The system can dynamically adjust the degree of parallelism in hierarchical decoding by choosing appropriate subsets, thereby achieving both high throughput and good error floor performance depending on channel conditions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the structural parameters of the base matrix to include cyclic shift elements and organizes them into subsets with different coding rates. This enables the system to optimize the balance between parallelism and error floor performance by selecting appropriate parameter configurations for different operating conditions.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If base matrix is optimized for ultra-high reliability, then error floor performance is improved, but device complexity increases

Engineering Contradiction:
Improveultra-high reliability transmissionVSAvoidbase matrix complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the base matrix into multiple subsets with different coding rates and organizes them systematically. This segmentation allows the system to achieve ultra-high reliability by selecting appropriate subsets without implementing a single overly complex base matrix, thereby managing device complexity through modular organization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent creates a universal base matrix structure that can serve multiple functions by including cyclic shift elements and organizing matrices into subsets. This universal structure can adapt to different reliability requirements and transmission conditions, achieving ultra-high reliability without proportionally increasing device complexity through its multi-functional design.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12542624B2Low density parity check coding and decoding methods, communication device, and storage medium
Publication Date: 2026.02.03 ZTE CORP
  • US12542624B2 patent drawing
  • US12542624B2 patent drawing
  • US12542624B2 patent drawing

AI summary

The present disclosure provides coding and decoding methods, a communication device, and a storage medium. The coding method, applied to a first transmission node, includes: determining a base matrix for low density parity check (LDPC) coding from a preset base matrix set; performing LDPC coding on original data according to the base matrix, so as to obtain coded data; transmitting the coded data to a second transmission node; wherein the base matrix includes two kinds of elements: an element indicating an all-zero square matrix, and an element indicating a cyclic shift of an identity matrix; the base matrix set includes at least two non-empty subsets of base matrices, and all base matrices in each subset of the at least two non-empty subsets of base matrices have a same coding rate.