Concatenated LDPC-BCH Decoding for Error Floor Reduction
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Solution Overview
Problem
Low-Density Parity-Check (LDPC) codes suffer from an error floor and slow convergence speed, which hampers their effectiveness in data protection and decoding processes, particularly in data communication and storage systems.
Innovation Solution
The proposed solution involves concatenating Bose—Chaudhuri—Hocquenghem (BCH) codes with Quasi-Cyclic (QC) LDPC codes and employing an iterative concatenated decoding process that includes both LDPC and BCH decoders, with a BCH scheduler to determine when to activate BCH decoding or syndrome calculation, thereby improving error correction and convergence speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDPC codes are used for error correction, then error correction capability is improved, but error floor problem occurs and convergence speed decreases
Solution Approach 1:
The patent segments the error correction task by dividing the code structure into two parts: an inner LDPC code for initial error correction and an outer BCH code for residual error correction. This segmentation allows each code to specialize in different error correction scenarios, with LDPC handling the bulk of error correction and BCH addressing the error floor problem, thereby improving overall convergence speed and reliability.
Solution Approach 2:
The patent creates a composite error correction system by concatenating LDPC codes with BCH codes. This composite structure combines the strengths of both coding schemes: the high error correction capability of LDPC codes and the proven performance of BCH codes in reducing error floors. The concatenated code achieves better convergence speed and lower error floors than either code alone.
2Reliability
If LDPC codes are used for data protection, then data integrity is improved, but system throughput decreases due to slow convergence
Solution Approach 1:
The patent applies preliminary action by using the LDPC code to perform initial error correction on the received data before the BCH decoding stage. This preliminary error correction reduces the number of errors that reach the BCH decoder, allowing the system to achieve data integrity faster and improve overall throughput by avoiding multiple iterative decoding cycles.
Solution Approach 2:
The patent introduces an intermediary component - the BCH code - that acts as a mediator between the noisy channel and the final data recovery process. The BCH code specifically targets and corrects residual errors that escape the LDPC decoding, serving as an intermediate correction layer that improves data integrity without significantly impacting system throughput.
3Ease of manufacture
If QC-LDPC codes are used for easier hardware implementation, then ease of manufacture is improved, but error floor problem persists
Solution Approach 1:
The patent merges QC-LDPC codes with BCH codes to create a concatenated coding scheme. This combination allows the system to maintain the hardware implementation advantages of QC-LDPC codes while adding BCH codes specifically to address the error floor problem. The merged system achieves both ease of manufacture and improved reliability.
Solution Approach 2:
The patent creates a composite error correction system by concatenating QC-LDPC codes with BCH codes. This composite structure combines the hardware-friendly properties of QC-LDPC codes with the error floor mitigation capabilities of BCH codes, achieving both ease of manufacture and reduced error floors.
Data Source
AI summary
Systems and methods are provided for concatenated error-correcting coding. An apparatus may include a Low-Density Parity-Check (LDPC) decoder configured to perform an iterative LDPC decoding process on bits of an LDPC codeword, a Bose—Chaudhuri—Hocquenghem (BCH) decoder coupled to the LDPC decoder and a BCH scheduler coupled to the LDPC decoder and the BCH decoder. The LDPC codeword may be generated by LDPC encoding a Bose—Chaudhuri—Hocquenghem (BCH) codeword and the BCH codeword may be generated by BCH encoding a data unit. The BCH scheduler may be configured to determine whether a triggering condition for the BCH decoder is met after each iteration of the iterative LDPC decoding process and activate the BCH decoder to operate on an intermediate decoding result of the LDPC decoder if the triggering condition for the BCH decoder is met.