Concatenated LDPC-BCH Decoding for Error Floor and Convergence
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Solution Overview
Problem
Low-Density Parity-Check (LDPC) codes suffer from an error floor and slow convergence speed, which hampers their effectiveness in data protection systems, particularly in hardware implementations like solid-state drives (SSDs).
Innovation Solution
The proposed solution involves concatenating Bose-Chaudhuri-Hocquenghem (BCH) codes with Quasi-Cyclic (QC) LDPC codes and employing an iterative concatenated decoding process that includes both LDPC and BCH decoders, with a BCH scheduler to determine when to activate BCH decoding or syndrome calculation, thereby improving error correction and convergence speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDPC codes are used for error correction, then error correction capability is improved, but error floor problem occurs and convergence speed decreases
Solution Approach 1:
The patent segments the error correction process into two distinct stages: first LDPC decoding iterations, then BCH decoding iterations. This segmentation allows each decoder to operate on intermediate results from the previous stage, with the BCH decoder specifically targeting residual errors that prevent LDPC convergence, thereby resolving the error floor issue without sacrificing overall convergence speed.
Solution Approach 2:
The patent implements periodic action by alternating between LDPC decoding iterations and BCH decoding iterations in a structured sequence. The controller performs a predetermined number of LDPC iterations, then switches to BCH iterations for a predetermined number of times, creating a periodic decoding pattern that systematically addresses different error types at different stages.
2Reliability
If more decoding iterations are performed to reduce error floor, then reliability is improved, but system throughput decreases
Solution Approach 1:
The patent applies dynamics by making the decoding process adaptive and conditional. The controller dynamically switches between LDPC and BCH decoding modes based on whether the LDPC syndrome is zero or non-zero. This dynamic approach ensures that BCH decoding is only activated when necessary (when residual errors exist), optimizing the balance between reliability improvement and throughput maintenance.
Solution Approach 2:
The patent changes the decoding parameters by switching between different decoding algorithms (LDPC vs. BCH) and adjusting the number of iterations for each based on syndrome results. The controller modifies the decoding strategy mid-process, transitioning from LDPC-only to a hybrid approach when error floor conditions are detected, thereby improving reliability without permanently increasing computational overhead.
Data Source
AI summary
Systems and methods are provided for concatenated error-correcting coding. An apparatus may include a Low-Density Parity-Check (LDPC) decoder configured to perform an iterative LDPC decoding process on bits of an LDPC codeword, a Bose-Chaudhuri-Hocquenghem (BCH) decoder coupled to the LDPC decoder and a BCH scheduler coupled to the LDPC decoder and the BCH decoder. The LDPC codeword may be generated by LDPC encoding a Bose-Chaudhuri-Hocquenghem (BCH) codeword and the BCH codeword may be generated by BCH encoding a data unit. The BCH scheduler may be configured to determine whether a triggering condition for the BCH decoder is met after each iteration of the iterative LDPC decoding process and activate the BCH decoder to operate on an intermediate decoding result of the LDPC decoder if the triggering condition for the BCH decoder is met.