LDPC-BCH Error Correction Switching for Faster TV Signal Decoding
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Solution Overview
Problem
In digital television broadcasting systems, the sequential LDPC error correction process often requires repeated iterations due to high error levels, significantly increasing the total time for error correction and degrading the performance of reception terminals.
Innovation Solution
An error correction apparatus and method that determines a stop time for the first error correction module (LDPC) based on the error correction capability of the second module (BCH), allowing the BCH to take over and reduce the overall error correction time by setting a termination condition associated with the BCH's maximum error correction capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDPC error correction is repeatedly performed to handle high error levels, then error correction completeness is improved, but total error correction time increases significantly
Solution Approach 1:
The patent segments the error correction process into two distinct stages: first performing LDPC error correction to reduce error levels to a manageable range, then switching to BCH error correction to complete the correction process. This segmentation allows each algorithm to operate in its optimal performance range, preventing the need for repeated LDPC iterations while ensuring complete error correction.
Solution Approach 2:
The patent implements a dynamic error correction strategy that adapts the correction algorithm based on the current error level. The system dynamically switches between LDPC and BCH algorithms according to the signal's error characteristics, using LDPC for high error levels and BCH for lower error levels, thereby optimizing both correction completeness and processing time.
2Reliability
If LDPC error correction is performed sequentially with multiple iterations, then error correction capability is improved, but processing speed deteriorates
Solution Approach 1:
The patent divides the error correction workload into two segments: LDPC handles the initial high-error correction phase, and BCH handles the final refinement phase. This segmentation prevents the need for multiple slow LDPC iterations by transitioning to the faster BCH algorithm once errors are reduced to a certain level, thereby maintaining high correction capability while improving processing speed.
Solution Approach 2:
The patent changes the error correction parameter (algorithm selection) based on the error level parameter. When the error level exceeds a threshold, LDPC is used; when it falls below the threshold, BCH is used. This parameter-based switching optimizes processing speed while maintaining adequate error correction capability for different signal conditions.
3Reliability
If the upper limit of LDPC correction times is increased, then error correction completeness is improved, but system performance deteriorates
Solution Approach 1:
The patent segments the error correction task between two algorithms with different characteristics. LDPC is used for a limited number of iterations to bring errors down to a manageable level, then BCH takes over to complete the correction. This segmentation eliminates the need to increase LDPC iteration limits, maintaining system performance while achieving complete error correction through the combined effort of both algorithms.
Solution Approach 2:
The patent introduces BCH error correction as an intermediary step between initial LDPC correction and final error-free output. BCH acts as a mediator that handles the remaining errors after LDPC has reduced the error level, allowing the system to achieve complete error correction without needing to excessively increase LDPC iteration limits, thus preserving system performance.
Data Source
AI summary
An error correction apparatus for a digital signal received by a signal reception terminal includes two error correction modules. The first error correction module performs first error correction on an input signal to generate an intermediate signal satisfying a termination condition. The second error correction module receives and selectively performs second error correction on the intermediate signal to generate a corrected signal. The termination condition is associated with a maximum error correction capability of the second error correction.


