LDPC BER Reporting With CRC-Terminated Parity Errors
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Solution Overview
Problem
Solid-state drives (SSDs) using multi-level NAND flash devices face reliability issues due to program disturb errors and inter-cell interference, requiring error correction codes that increase data reliability but also consume extra storage space, necessitating improved error correction methods for enhanced decoding performance.
Innovation Solution
A method and system for LDPC decoding using a quasi-cyclic matrix with multiple circulant columns, where messages for variable and check nodes are computed, cyclic redundancy check (CRC) parity and syndrome are calculated, and bit error rate (BER) is determined in different modes to assess decoding accuracy and error presence in user and parity portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction codes are used to increase data reliability, then data reliability is improved, but extra storage space is consumed for ECC parity bits
Solution Approach 1:
The LDPC codeword is segmented into user data bits and parity bits, with the parity portion further divided into multiple circulant columns. This segmentation allows selective processing and error detection in different portions of the code, improving overall reliability while optimizing storage utilization.
Solution Approach 2:
The patent employs a quasi-cyclic LDPC matrix structure with specific parameter configurations (circulant column size, number of circulant columns) that optimize the balance between error correction capability and storage efficiency. By adjusting these parameters, the system achieves improved data reliability without proportionally increasing storage space requirements.
2Measurement precision
If BER calculation is performed in both first mode (no parity errors) and second mode (parity errors present), then decoding accuracy is improved, but computational complexity increases
Solution Approach 1:
The BER calculation process dynamically adapts between two modes based on the presence or absence of parity errors. The system transitions between calculation modes depending on the decoding state, optimizing computational resources while maintaining high decoding accuracy across different error conditions.
Solution Approach 2:
The system uses feedback from CRC parity checks and syndrome calculations to determine which BER calculation mode to employ. This feedback mechanism allows the system to select the appropriate calculation complexity based on the actual error state, improving decoding accuracy without consistently incurring maximum computational overhead.
3Quantity of substance
If multi-level NAND flash devices are used for persistent storage, then storage capacity is increased, but program disturb errors and inter-cell interference increase
Solution Approach 1:
The patent applies LDPC error correction coding beforehand to cushion against the harmful effects of program disturb errors and inter-cell interference that will occur in multi-level NAND flash devices. This preventive error correction mechanism protects data integrity despite the increased susceptibility to errors in high-capacity storage devices.
Solution Approach 2:
The system uses a composite approach combining multiple error detection and correction techniques (LDPC coding, CRC parity, syndrome calculation) to protect against the various harmful factors affecting multi-level NAND flash devices. This composite error protection strategy addresses the complex error patterns arising from program disturb and inter-cell interference.
Data Source
AI summary
A method and system for LDPC decoding method. In the method and system, an LDPC codeword is decoded using a quasi-cyclic matrix. A first message for variable nodes in a circulant column of the quasi-cyclic matrix and a second message for check nodes belonging to the circulant column are computed. Parity and syndrome are computed using the computed first and second messages. A bit error rate is calculated for both a first mode with no error in a parity portion of a codeword and a second mode with errors in the parity portion of the codeword.