LDPC Bit-Group Interleaver for Burst Error Distribution in BICM
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems suffer from rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver optimized for an LDPC coder with a length of 64800 and code rate of 3/15, using 16-symbol mapping, is designed to effectively distribute burst errors by interleaving the LDPC codeword on a bit group basis, with a specific permutation order, and integrated into a BICM device for next-generation broadcasting systems like ATSC 3.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors in the channel cause rapid performance degradation
Solution Approach 1:
The bit interleaver divides the LDPC codeword into multiple bit groups (180 groups of 360 bits each) and applies permutation to each group independently. This segmentation allows the system to handle burst errors more effectively while maintaining a manageable design complexity through modular processing
Solution Approach 2:
The patent optimizes the permutation order parameters specifically for 16-symbol mapping and LDPC code rate 3/15. By tuning these parameters to match the specific system configuration, the interleaver achieves optimal error distribution performance without requiring overly complex adaptive mechanisms
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then error correction performance improves, but the system loses flexibility in adapting to different configurations
Solution Approach 1:
The patent establishes optimized permutation orders for specific configurations (16-symbol mapping, code rate 3/15, block length 64800). These parameter-specific optimizations deliver superior error correction performance while the underlying interleaver structure remains adaptable to different BICM configurations through parameter reconfiguration
3Reliability
If burst errors are not distributed, then the system structure remains simple, but performance degrades rapidly in noisy channels
Solution Approach 1:
By dividing the codeword into 180 bit groups and applying permutation to distribute errors across groups, the system achieves effective burst error handling. The segmented approach prevents performance degradation while keeping the interleaving structure manageable through systematic organization
Solution Approach 2:
The bit interleaver acts as an intermediary component between the LDPC encoder and 16-symbol modulator. It receives the encoded bit stream, applies permutation to distribute burst errors, and outputs the interleaved stream to the modulator, thereby protecting the system from channel-induced error bursts
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.