LDPC Bit Group Interleaver for Burst Error Distribution in BICM
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems suffer from rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver is designed for an LDPC coder with a length of 64800 and code rate of 3/15, using a processor to generate an interleaved codeword on a bit group basis, with a specific permutation order for effective distribution of burst errors, and outputting the interleaved codeword for 64-symbol mapping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a bit-by-bit interleaver is used in BICM systems, then bandwidth efficiency is improved through high-order modulation, but performance degrades rapidly due to burst errors in digital broadcast channels
Solution Approach 1:
The patent segments the codeword into multiple bit groups (e.g., 360 bits per group for LDPC code length 64800) and performs interleaving at the bit group level rather than individual bit level. This segmentation allows the system to maintain bandwidth efficiency through high-order modulation while distributing burst errors across multiple bit groups, preventing catastrophic failure of entire codewords.
Solution Approach 2:
The patent introduces a new dimension of interleaving organization by using bit group-based permutation with specific patterns (e.g., alternating even-odd group arrangements). This dimensional reorganization of data flow transforms how burst errors propagate through the system, converting concentrated errors into distributed errors that can be corrected by the LDPC decoder.
2Device complexity
If a simple interleaver structure is used, then device complexity is reduced, but the ability to distribute burst errors is insufficient
Solution Approach 1:
The patent divides the codeword into bit groups and applies segmentation-based interleaving where even-indexed groups and odd-indexed groups are separated and repositioned according to a permutation pattern. This segmented approach achieves effective burst error distribution without requiring complex memory structures or multiple interleaving stages.
Solution Approach 2:
The patent performs preliminary organization of bit groups into even and odd sequences before the main interleaving operation. This preliminary action simplifies the subsequent permutation step and enables efficient implementation with reduced computational complexity while maintaining strong burst error distribution properties.
3Reliability
If bit group-based interleaving with specific permutation order is implemented, then burst error distribution is optimized, but device complexity increases
Solution Approach 1:
The patent pre-calculates and stores the permutation order table for bit group interleaving, which can be implemented as a simple lookup operation during transmission. This preliminary preparation transforms a potentially complex real-time computation into a simple table-driven process, optimizing burst error distribution while minimizing runtime device complexity.
Solution Approach 2:
The patent employs periodic patterns in the bit group interleaving, such as alternating between even and odd group sequences in a regular pattern. This periodic structure enables efficient implementation using simple counters and pattern generators rather than complex arbitrary permutation logic, achieving optimal burst error distribution with minimal processing complexity.
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.