LDPC Bit Interleaving for Burst Error Distribution in 16-Symbol Mapping
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver is designed for an LDPC coder with a length of 64800 and code rate of 3/15, using a processor to generate an interleaved codeword on a bit group basis, with a specific permutation order for effective distribution of burst errors, and outputting the interleaved codeword for 16-symbol mapping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors in the channel cause rapid performance degradation
Solution Approach 1:
The bit interleaver divides the codeword into multiple bit groups and applies different permutation patterns to different segments. This segmentation allows the system to handle burst errors more effectively by distributing them across different segments, preventing concentrated error clusters that would degrade performance
Solution Approach 2:
The patent applies different permutation patterns to different bit groups based on their position and characteristics. This local quality approach optimizes error distribution for specific regions of the codeword, enhancing overall system reliability without requiring complete redesign of the entire interleaving structure
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then performance improves, but the adaptability to different broadcasting standards decreases
Solution Approach 1:
The patent employs configurable parameters including parallel factor, number of bit groups, and permutation patterns that can be adjusted according to different modulation orders and code rates. This parameter-based design allows the same interleaver structure to be adapted to various broadcasting standards and requirements while maintaining optimized performance
3Reliability
If burst errors are not distributed, then the interleaver structure remains simple, but error correction capability deteriorates rapidly
Solution Approach 1:
The bit interleaver performs preliminary distribution of bits into different groups and applies permutation patterns before transmission. This preliminary action ensures that burst errors occurring during transmission are already dispersed across different bit groups, enhancing error correction capability before the decoder processes the signal
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.