LDPC Bit Interleaver Layout for Burst Error Distribution
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver is designed for an LDPC coder with a length of 64800 and code rate of 5/15, using 64-symbol mapping, which interleaves the LDPC codeword on a bit group basis with a specific permutation order to effectively distribute burst errors, suitable for next-generation broadcasting systems like ATSC 3.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors in the channel cause rapid performance degradation
Solution Approach 1:
The patent segments the 64800-bit LDPC codeword into multiple bit groups of 360 bits each (64800/360 = 180 groups). This segmentation allows the interleaver to process and distribute burst errors more effectively by operating on manageable units while maintaining overall system reliability. The segmented approach prevents performance degradation by ensuring that burst errors are spread across different bit groups rather than concentrated in one location.
Solution Approach 2:
The patent applies specific parameter changes to the interleaver design, including setting the parallel factor to 360 and using a specifically designed permutation order for bit group interleaving. These parameter optimizations are tailored for 64-symbol mapping and LDPC codes with length 64800 and code rate 5/15, achieving better error distribution performance without excessive complexity increase.
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then error distribution performance improves, but the system loses flexibility
Solution Approach 1:
The patent designs a universal bit interleaver structure that can handle LDPC codes with length 64800 and code rate 5/15 combined with 64-symbol mapping. The interleaver uses a parallel factor of 360 and processes bit groups of 360 bits, creating a flexible framework that maintains good error distribution performance while being applicable to next-generation broadcasting systems. The design achieves a balance between optimization for specific parameters and broader applicability.
3Productivity
If burst errors are not distributed, then the system structure remains simple, but performance degrades rapidly in broadcast channels
Solution Approach 1:
The patent implements preliminary bit group interleaving before modulation, using a predetermined permutation order for the 180 bit groups. This preliminary action distributes burst errors across different bit groups before they enter the modulation stage, preventing performance degradation. The interleaving operation is performed in advance on the structured bit groups, making the error distribution efficient without adding excessive complexity during the main transmission process.
Data Source
AI summary
A bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 5/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.