LDPC Bit-Flip Voting for High-Density NAND Error Correction
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Solution Overview
Problem
As NAND flash memory density increases, bit error rates also rise, making existing BCH error correction codes inadequate for reliable data decoding in solid-state storage devices, especially in enterprise computing applications.
Innovation Solution
Implementing a hybrid decoding system that uses a hard-decision Low Density Parity Check (LDPC) decoder with a voting scheme and a Bose-Chaudhuri-Hocquenghem (BCH) decoder to reduce errors in data, where the LDPC decoder selects a voting scheme at each iteration to determine bit flipping based on a variable node's connectivity and an adjustment value, improving error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If NAND flash memory density is increased, then storage capacity is improved, but bit error rate increases making error correction more difficult
Solution Approach 1:
The patent combines LDPC decoding and BCH decoding into a hybrid error correction system. The LDPC decoder first reduces the error rate of read data, and then the BCH decoder further corrects remaining errors. This merging of two different error correction approaches enables the system to handle the increased error rates from high-density NAND flash while maintaining reliable data recovery.
2Reliability
If BCH code correction capability is increased to handle higher error rates, then error correction capability is improved, but system complexity and processing burden increase
Solution Approach 1:
The error correction process is segmented into two distinct stages: first, the LDPC decoder performs initial error reduction on the read data, and second, the BCH decoder performs final error correction. This segmentation allows each decoder to be optimized for its specific function, with the LDPC decoder handling the bulk of error reduction and the BCH decoder focusing on correcting remaining errors, thereby distributing the processing burden more effectively.
Solution Approach 2:
The LDPC decoder performs preliminary error reduction before the BCH decoder operates. By pre-processing the data to reduce the error rate, the LDPC decoder eases the burden on the BCH decoder, allowing it to work with fewer errors and achieve better correction results with reduced computational complexity.
3Reliability
If BCH code is designed to correct more errors, then error correction capability is improved, but the code becomes less scalable and economically feasible
Solution Approach 1:
The hybrid LDPC-BCH decoding system provides universal error correction capability that adapts to different NAND flash density requirements. The LDPC component can be configured with various code rates and block lengths, while the BCH component handles residual errors, creating a flexible system that can economically scale across different memory densities and application requirements.
Data Source
AI summary
A solid state storage device comprises a non-volatile memory controller configured to store data in a non-volatile memory, wherein the stored data is encoded using a first error-correcting code and a second Low Density Parity Check (LDPC) code. The non-volatile memory controller includes a hard-decision LDPC decoder to decode encoded data received from the non-volatile memory and provide a decoded data output. The hard-decision LDPC decoder selects a voting scheme at each iteration in a sequence of iterations of decoding to determine when to implement bit flipping at a variable node amongst a plurality of check nodes, each of the plurality of check nodes connected to a plurality of variable nodes.