Neural-Network LDPC Bit Flipping for Better BER Decoding

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Solution Overview

Problem

Existing bit flipping decoders for Low Density Parity Check (LDPC) codes rely on heuristic rules for error correction, which are challenging to optimize, especially for irregular codes, leading to suboptimal bit error rate (BER) performance.

Innovation Solution

A neural network is trained for bit flipping decisions, using feature maps generated during decoding iterations, to determine whether bits should be flipped based on input from variable nodes, improving BER performance by reducing reliance on heuristic rules.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If heuristic rules are used for bit flipping decisions, then the implementation is simple and area/power savings are achieved, but the BER performance is suboptimal

Engineering Contradiction:
ImproveBER performanceVSAvoiddecoder complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces the mechanical/heuristic rule-based bit flipping system with a neural network-based system. The neural network learns optimal bit flipping decisions through training on labeled data, substituting the manual heuristic approach with a data-driven machine learning model that achieves superior BER performance while maintaining hardware implementability.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the fundamental parameter of bit flipping decision-making from fixed heuristic rules to dynamic neural network predictions. By training the neural network on diverse LDPC code instances and error patterns, the system adapts its parameters (weights and biases) to optimize BER performance across different code configurations rather than relying on static heuristic thresholds.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If heuristic rules are optimized for irregular LDPC codes, then BER performance may improve, but the rule generation becomes extremely challenging

Engineering Contradiction:
ImproveBER performanceVSAvoidrule generation difficulty
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies self-service by enabling the neural network to automatically learn optimal bit flipping strategies through training on labeled training sets. Instead of requiring manual heuristic rule generation and optimization, the system trains itself on diverse LDPC code instances and error patterns, automatically adapting to irregular code structures without human intervention in rule creation.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent performs preliminary action by training the neural network offline on comprehensive training data that includes various irregular LDPC code configurations and error patterns. This pre-training phase allows the network to learn robust bit flipping strategies before deployment, eliminating the need for complex real-time rule generation and optimization during actual decoding operations.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If message passing decoders are used, then good error correction capability is achieved, but the silicon implementation becomes complex

Engineering Contradiction:
Improveerror correction capabilityVSAvoidsilicon implementation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the complex message passing computations and replaces them with a simplified neural network-based bit flipping approach. By taking out the intricate message passing algorithms and substituting them with a more straightforward neural network model, the system maintains good error correction capability while significantly reducing silicon implementation complexity and resource requirements.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS10491243B2Deep learning for low-density parity-check (LDPC) decoding
Publication Date: 2019.11.26 SK HYNIX INC
  • US10491243B2 patent drawing
  • US10491243B2 patent drawing
  • US10491243B2 patent drawing

AI summary

Techniques for improving the bit error rate (BER) performance of an error correction system are described. In an example, the error correction system implements low-density parity-check (LDPC) decoding that uses bit flipping. In a decoding iteration, a feature map is generated for a bit of an LDPC codeword. The bit corresponds to a variable node. The feature map is input to a neural network that is trained to determine whether bits should be flipped based on corresponding feature maps. An output of the neural network is accessed. The output indicates that the bit should be flipped based on the feature map. The bit is flipped in the decoding iteration based on the output of the neural network.