LDPC Bit-Flipping Decoder with Checksum-Aided Error Reduction
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Solution Overview
Problem
Bit-flipping (BF) decoding algorithms for LDPC codes in SSD applications face performance limitations, particularly in mobile and client SSDs, due to their inferior error correction performance compared to other decoding methods like sum-product or min-sum algorithms, while requiring low power consumption.
Innovation Solution
A checksum-aided error reduction (CA-ER) scheme is integrated into the bit-flipping decoder to enhance decoding performance by updating hard decision values and applying error recovery based on checksum conditions, improving decoding efficiency without increasing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If bit-flipping decoding algorithm is used, then power consumption is reduced, but decoding performance deteriorates
Solution Approach 1:
The decoding process is divided into two distinct phases: a first decoding phase using the bit-flipping algorithm for initial error correction, and a second decoding phase using a more sophisticated algorithm for residual error correction. This segmentation allows the system to leverage the low power consumption of BF decoding while ultimately achieving the performance of more complex algorithms through selective application of different decoding strategies at different stages.
Solution Approach 2:
The bit-flipping decoding is performed as a preliminary action before applying more complex decoding algorithms. By first using the computationally simple BF algorithm to correct obvious errors, the system reduces the error burden before engaging more power-intensive decoding methods, thereby optimizing the overall power-performance tradeoff.
2Reliability
If more complex decoding algorithms are used, then decoding performance is improved, but power consumption increases
Solution Approach 1:
The decoding workload is segmented into two phases with different algorithmic complexities. The first phase uses simple bit-flipping operations that consume minimal power, while the second phase employs more complex algorithms only when necessary. This segmentation ensures that high-performance decoding is achieved only when the error patterns require it, rather than always deploying computationally intensive algorithms.
Solution Approach 2:
Instead of always applying full-strength complex decoding algorithms, the system applies them partially or selectively only after the first decoding phase fails to fully correct errors. This partial application of complex algorithms reduces overall power consumption while still achieving sufficient decoding performance for the remaining uncoded bits.
3Use of energy by moving object
If first decoding phase is performed, then power consumption is reduced, but error correction completeness deteriorates
Solution Approach 1:
The decoding process maintains continuity by seamlessly transitioning from the first bit-flipping decoding phase to the second decoding phase. Rather than treating them as separate independent operations, the system continuously processes errors through both phases, ensuring that useful error correction action continues without interruption until all correctable errors are resolved or the maximum correction capacity is reached.
Solution Approach 2:
The first bit-flipping decoding phase serves as a preliminary error correction action that prepares the data for the second phase. By addressing easily correctable errors first, it reduces the error burden before the second phase tackles more challenging error patterns, thereby improving overall error correction completeness without requiring the second phase to handle all errors from scratch.
Data Source
AI summary
Memory controllers bit-flipping (BF) decoders and methods that selectively apply a checksum-aided error reduction (CA-ER) scheme to BF decoding of a low-density parity-check (LDPC) code. In decoding a codeword, a hard decision value resulting from decoding a select variable node is changed when a first condition is satisfied to yield an updated hard decision value. Also, when the first condition is satisfied, a current checksum value after processing the select variable node is updated using the updated hard decision value. The CA-ER scheme is applied when the updated checksum value is not reduced to a set minimum and a second condition based on a previous checksum value, calculated after a previous variable node is processed, is satisfied.