LDPC Decoder Bit Flipping with Hard Decisions and Erasures

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Solution Overview

Problem

Existing LDPC hard decision algorithms are inefficient in processing and storing soft information, which limits their decoding performance due to high demands on processor and memory resources.

Innovation Solution

A method for decoding data using hard decisions and erasures, where circuitry processes values from variable nodes based on specific processing rules, combining indications of conditions stored in check nodes, and optimizing memory usage by combining multiple nodes into blocks, allowing for three-state inputs and efficient storage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If soft information is used for decoding, then decoding performance is improved, but processor and memory resource demands increase significantly

Engineering Contradiction:

Improvedecoding performanceVSAvoidprocessor and memory resource demands

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the continuous soft information into discrete hard decisions (0 or 1) and erasure states. Each variable node is divided into distinct states based on threshold comparisons, transforming continuous probability distributions into discrete categories that are easier to process and store without significant loss of decoding performance.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes the parameter representation from continuous soft information (probability distributions) to discrete states (hard decisions and erasures). By introducing threshold parameters that convert continuous values into discrete categories, the system reduces memory requirements while maintaining effective error correction capabilities.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If three-state values are stored in variable nodes, then error correction capability is improved, but memory storage requirements increase

Engineering Contradiction:

Improveerror correction capabilityVSAvoidmemory storage requirements

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The patent merges multiple variable nodes into blocks, where each block shares common check nodes. This combining approach allows the system to process and store three-state values efficiently by grouping nodes, reducing the overall memory footprint while maintaining the error correction benefits of multi-state representation.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces a block dimension to the memory structure, organizing variable nodes into blocks rather than storing them individually. This dimensional reorganization allows efficient storage of three-state values by exploiting the shared structure among nodes within each block, reducing redundant storage requirements.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8667361B1Systems and methods for performing bit flipping in an LDPC decoder

Publication Date: 2014.03.04 MARVELL ASIA PTE LTD

AI summary

Systems and methods are provided for decoding data using hard decisions and erasures. Circuitry receives data from each of a plurality of variable nodes which correspond to bits of data being decoded. Each variable node stores one of at least three values. The circuitry determines processes the values received from the plurality of variable nodes according to a set of processing rules. The processing rules are used to determine a condition related to the values stored by the plurality of variable nodes. The circuitry stores an indication of the stored condition at a check node.