LDPC Memory Controller Bit-Flipping for Trapping Status Recovery
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional LDPC decoders using bit-flipping algorithms often enter a trapping status during decoding, leading to repeated iterative operations and reduced decoding performance due to increased error floors.
Innovation Solution
A memory controller with a variable-node circuit and check-node circuit that detects trapping status through a threshold-tracking circuit, switching from a first flipping strategy to a post-processing flipping strategy to escape trapping, thereby improving decoding performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional bit-flipping algorithms are used for LDPC decoding, then the decoding process can be implemented with simple hardware, but the decoder enters trapping status causing repeated iterative operations and reduced decoding performance
Solution Approach 1:
The patent applies preliminary action by detecting the trapping status before the decoder completes normal operation. The threshold-tracking circuit monitors variable node thresholds in advance to identify when the decoder enters trapping status, allowing early intervention with post-processing bit-flipping to prevent repeated iterative operations and improve decoding reliability
Solution Approach 2:
The patent implements feedback through the threshold-tracking circuit that continuously monitors variable node thresholds and provides feedback signals to the control logic. This feedback mechanism detects when thresholds exceed predetermined thresholds, indicating trapping status, and triggers appropriate corrective actions to maintain decoding performance
2Measurement precision
If the decoder operates for extended iterative operations to ensure accurate decoding, then decoding accuracy improves, but the time required for decoding increases due to repeated operations in trapping status
Solution Approach 1:
The patent applies skipping by detecting trapping status through threshold monitoring and rapidly transitioning to post-processing bit-flipping mode. This allows the decoder to skip through the problematic repeated iterative operations that would otherwise consume excessive time, maintaining decoding accuracy while significantly reducing decoding time by bypassing the trapping cycle
Data Source
AI summary
A memory controller for use in a data storage device is provided. The memory controller includes a variable-node circuit and a check-node circuit. The check-node circuit obtains a codeword difference from the variable-node circuit, and calculates a syndrome according to the codeword difference. The variable-node circuit includes a threshold-tracking circuit which is configured to track a threshold used by the variable-node circuit during a low-density parity check (LDPC) decoding process to determine whether the variable-node circuit has entered a trapping status. In response to determining that the variable-node circuit has entered the trapping status during the LDPC decoding process, the variable-node circuit switches a bit-flipping algorithm used by the variable-node circuit during the LDPC decoding process from a first flipping strategy to a post-processing flipping strategy to bring the variable-node circuit out of the trapping status. The first flipping strategy is different from the post-processing flipping strategy.